SLVSBA5D October   2012  – April 2016 DRV8313

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Stage
      2. 7.3.2 Bridge Control
      3. 7.3.3 Charge Pump
      4. 7.3.4 Comparator
      5. 7.3.5 Protection Circuits
        1. 7.3.5.1 Undervoltage Lockout (UVLO)
        2. 7.3.5.2 Thermal Shutdown (TSD)
        3. 7.3.5.3 Overcurrent Protection (OCP)
    4. 7.4 Device Functional Modes
      1. 7.4.1 nRESET and nSLEEP Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Three-Phase Brushless-DC Motor Control
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Motor Voltage
          2. 8.2.1.2.2 Motor Commutation
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Three-Phase Brushless-DC Motor Control With Current Monitor
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Trip Current
          2. 8.2.2.2.2 Sense Resistor
      3. 8.2.3 Brushed-DC and Solenoid Load
        1. 8.2.3.1 Design Requirements
          1. 8.2.3.1.1 Detailed Design Procedure
      4. 8.2.4 Three Solenoid Loads
        1. 8.2.4.1 Design Requirements
          1. 8.2.4.1.1 Detailed Design Procedure
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
      1. 10.3.1 Heatsinking
    4. 10.4 Power Dissipation
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

PWP Package
28-Pin HTSSOP With PowerPAD Package
Top View
NC - No internal connection
RHH Package
36-Pin VQFN With Exposed Thermal Pad
Top View

Pin Functions

PIN TYPE(1) DESCRIPTION
NAME NO.
PWP RHH
COMPN 13 22 I Comparator negative input. Uncommitted comparator input
COMPP 12 21 I Comparator positive input. Uncommitted comparator input
CPL 1 5 PWR Charge pump. Connect a VM-rated, 0.01-µF ceramic capacitor between CPH and CPL.
CPH 2 6 PWR Charge pump. Connect a VM-rated, 0.01-µF ceramic capacitor between CPH and CPL.
EN1 26 1 I Channel enable. Logic high enables the 1/2-H bridge channel; internal pulldown
EN2 24 35 I Channel enable. Logic high enables the 1/2-H bridge channel; internal pulldown
EN3 22 33 I Channel enable. Logic high enables the 1/2-H bridge channel; internal pulldown
GND 14, 20, 28 3, 17, 20, 23, 24, 30, 31, 32, PWR Device ground. Connect to system ground
IN1 27 2 I Channel input. Logic high pulls 1/2-H bridge high, logic low pulls 1/2-H bridge low; no effect when ENx is low; internal pulldown input.
IN2 25 36 I Channel input. Logic high pulls 1/2-H bridge high, logic low pulls 1/2-H bridge low; no effect when ENx is low; internal pulldown input.
IN3 23 34 I Channel input. Logic high pulls 1/2-H bridge high, logic low pulls 1/2-H bridge low; no effect when ENx is low; internal pulldown input.
NC 21 4, 8, 14 NC No internal connection. Recommended net given in block diagram (if any)
nCOMPO 19 29 OD Comparator output. Uncommitted comparator output; open drain requires an external pullup.
nFAULT 18 28 OD Fault indication pin. Pulled logic-low with fault condition; open-drain output requires an external pullup.
nRESET 16 26 I Reset input. Active-low reset input initializes internal logic, clears faults, and disables the outputs, internal pulldown
nSLEEP 17 27 I Sleep mode input. Logic high to enable device; logic low to enter low-power sleep mode; internal pulldown
OUT1 5 10 O Half-H bridge output, connect to the load
OUT2 8 13 O Half-H bridge output, connect to the load
OUT3 9 15 O Half-H bridge output, connect to the load
PGND1 6 11 PWR Low-side FET source. Connect to GND or to low-side current-sense resistors
PGND2 7 12 PWR Low-side FET source. Connect to GND or to low-side current-sense resistors
PGND3 10 16 PWR Low-side FET source. Connect to GND or to low-side current-sense resistors
RSVD — 18 — Reserved. Leave this pin disconnected.
V3P3 15 25 PWR Internal regulator. Internal supply voltage; bypass to GND with a 6.3-V, 0.47-µF ceramic capacitor; up to 10-mA external load
VCP 3 7 PWR Charge pump. Connect a 16-V, 0.1-µF ceramic capacitor to VM
VM 4, 11 9, 19 PWR Power supply. Connect to motor supply voltage; bypass to GND with two 0.1-µF capacitors (for each pin) plus one bulk capacitor rated for VM
Thermal pad PWR Must be connected to ground