JAJSI17D November   2013  – October 2019 DRV8850

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Supervisor
      2. 7.3.2 Bridge Control
      3. 7.3.3 Current Sensing – VPROPI
      4. 7.3.4 Slew-Rate Control
      5. 7.3.5 Dead Time
      6. 7.3.6 Propagation Delay
      7. 7.3.7 Power Supplies and Input Pins
      8. 7.3.8 LDO Voltage Regulator
      9. 7.3.9 Protection Circuits
        1. 7.3.9.1 Overcurrent Protection (OCP)
        2. 7.3.9.2 Thermal Shutdown (TSD)
        3. 7.3.9.3 Undervoltage Lockout (UVLO)
        4. 7.3.9.4 Overvoltage Lockout (OVLO)
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Motor Voltage
        2. 8.2.2.2 Drive Current
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
      1. 10.3.1 Power Dissipation
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.1 Power Supervisor

The LDO regulator can be active independent of the nSLEEP pin. This independence allows a microcontroller, or other device, to be powered by the LDO voltage regulator, while retaining the ability to put the DRV8850 device into sleep mode.

Because of this functionality, nSLEEP and LDOEN must both be brought logic low to minimize power consumption in sleep mode. If the LDO regulator remains active in sleep mode, a quiescent current of IVCQ2 (typically 50 µA plus current through the external feedback resistors) is drawn from the supply.

Table 2 lists the operation mode logic for the DRV8850 device.

Table 2. DRV8850 Device Operation Mode Logic(1)

nSLEEP LDOEN LDO REGULATOR DRIVER
0 0 Off Sleep
0 1 Active Sleep
1 0 Off Active
1 1 Active Active
(1) A state must be active for a minimum of 1 ms before a new state is commanded.