SLVSD18C June   2015  – August 2017 DRV8880

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified System Diagram
      2.      Microstepping Current Waveform
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Indexer Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Stepper Motor Driver Current Ratings
        1. 7.3.1.1 Peak Current Rating
        2. 7.3.1.2 RMS Current Rating
        3. 7.3.1.3 Full-Scale Current Rating
      2. 7.3.2  PWM Motor Drivers
      3. 7.3.3  Microstepping Indexer
      4. 7.3.4  Current Regulation
      5. 7.3.5  Decay Modes
        1. 7.3.5.1 Mode 1: Slow Decay for Increasing and Decreasing Current
        2. 7.3.5.2 Mode 2: Slow Decay for Increasing Current, Mixed Decay for Decreasing current
        3. 7.3.5.3 Mode 3: Mixed Decay for Increasing and Decreasing Current
        4. 7.3.5.4 Mode 4: Slow Decay for Increasing Current, Fast Decay for Decreasing current
        5. 7.3.5.5 Mode 5: Fast Decay for Increasing and Decreasing Current
      6. 7.3.6  Smart Tune
      7. 7.3.7  Adaptive Blanking Time
      8. 7.3.8  Charge Pump
      9. 7.3.9  LDO Voltage Regulator
      10. 7.3.10 Logic and Tri-Level Pin Diagrams
      11. 7.3.11 Power Supplies and Input Pins
      12. 7.3.12 Protection Circuits
      13. 7.3.13 VM UVLO (UVLO2)
      14. 7.3.14 Logic Undervoltage (UVLO1)
      15. 7.3.15 VCP Undervoltage Lockout (CPUV)
      16. 7.3.16 Thermal Shutdown (TSD)
      17. 7.3.17 Overcurrent Protection (OCP)
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Stepper Motor Speed
        2. 8.2.2.2 Current Regulation
        3. 8.2.2.3 Decay Modes
        4. 8.2.2.4 Sense Resistor
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance Sizing
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RHR|28
  • PWP|28
サーマルパッド・メカニカル・データ
発注情報

7.3.17 Overcurrent Protection (OCP)

An analog current limit circuit on each FET limits the current through the FET by removing the gate drive. If this analog current limit persists for longer than tOCP, all FETs in the H-bridge will be disabled and nFAULT will be driven low. In addition to this FET current limit, an overcurrent condition is also detected if the voltage at xISEN exceeds VOCP.

The overcurrent fault response can be set to either latched mode or retry mode:

DRV8880 latched_OCP_mode_lvsd18.gifFigure 25. Latched OCP Mode
DRV8880 retry_OCP_mode_lvsd18.gifFigure 26. Retry OCP Mode

In latched mode, operation will resume after the ENABLE pin is brought logic low for at least 1 μs to reset the output driver. The nFAULT pin will be released after ENABLE is returned logic high. Removing and re-applying VM or toggling nSLEEP will also reset the latched fault.

In retry mode, the driver will be re-enabled after the OCP retry period (tRETRY) has passed. nFAULT becomes high again after the retry time. If the fault condition is still present, the cycle repeats. If the fault is no longer present, normal operation resumes and nFAULT remains deasserted.

A microcontroller can retain control of the ENABLE pin while in retry mode if it is operated like an open-drain output. Many microcontrollers support this. When the DRV8880 is operating normally, configure the MCU GPIO as an input. In this state, the MCU can detect whenever nFAULT is pulled low. In order to disable the DRV8880 output, configure the GPIO output state as low, and then configure the GPIO as an output.

Alternatively, a logic-level FET may be used to create an open drain external to the MCU. In this case, an additional MCU GPIO may be required in order to monitor the nFAULT pin.

DRV8880 OCP_addl_GPIO_lvsd18.gifFigure 27. Methods For Operating in Retry Mode

Table 10. Fault Condition Summary

FAULT CONDITION ERROR REPORT H-BRIDGE CHARGE PUMP INDEXER V3P3 RECOVERY
VM undervoltage
(UVLO2)		 VM < VUVLO2
(max 6.4 V)		 nFAULT Disabled Disabled Operating
Operating
VM > VUVLO2
(max 6.5 V)
Logic undervoltage
(UVLO1)		 VM < VUVLO2
(max 4.9 V)		 None Disabled Disabled Disabled
Operating
VM > VUVLO2
(max 4.8 V)
VCP undervoltage
(CPUV)		 VCP < VCPUV
(typ VM + 1.8 V)		 nFAULT Disabled Operating Operating
Operating
VCP > VCPUV
(typ VM + 1.9 V)
Thermal Shutdown
(TSD)		 TJ > TTSD
(min 150°C)		 nFAULT Disabled Operating Operating
Operating
TJ < TTSD - THYS
(THYS typ 35°C)
Overcurrent
(OCP)		 IOUT > IOCP
(min 2.5 A)
VxISEN > VOCP
(min 0.9 V)		 nFAULT Disabled Operating Operating
Operating
ENABLE
-or-
tRETRY