JAJSCW7D January   2016  – November 2018 DRV8884

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
      2.      マイクロステッピング電流の波形
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Indexer Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Stepper Motor Driver Current Ratings
        1. 8.3.1.1 Peak Current Rating
        2. 8.3.1.2 RMS Current Rating
        3. 8.3.1.3 Full-Scale Current Rating
      2. 8.3.2  PWM Motor Drivers
      3. 8.3.3  Microstepping Indexer
      4. 8.3.4  Current Regulation
      5. 8.3.5  Controlling RREF With an MCU DAC
      6. 8.3.6  Decay Modes
        1. 8.3.6.1 Mode 1: Slow Decay for Increasing and Decreasing Current
        2. 8.3.6.2 Mode 2: Slow Decay for Increasing Current, Mixed Decay for Decreasing Current
        3. 8.3.6.3 Mode 3: Mixed Decay for Increasing and Decreasing Current
      7. 8.3.7  Blanking Time
      8. 8.3.8  Charge Pump
      9. 8.3.9  LDO Voltage Regulator
      10. 8.3.10 Logic and Multi-Level Pin Diagrams
      11. 8.3.11 Protection Circuits
        1. 8.3.11.1 VM UVLO
        2. 8.3.11.2 VCP Undervoltage Lockout (CPUV)
        3. 8.3.11.3 Overcurrent Protection (OCP)
        4. 8.3.11.4 Thermal Shutdown (TSD)
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Stepper Motor Speed
        2. 9.2.2.2 Current Regulation
        3. 9.2.2.3 Decay Modes
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Bulk Capacitance
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.9 LDO Voltage Regulator

An LDO regulator is integrated into the DRV8884. DVDD can be used to provide a reference voltage. For proper operation, bypass DVDD to GND using a ceramic capacitor.

The DVDD output is nominally 3.3 V. When the DVDD LDO current load exceeds 1 mA, the output voltage drops significantly.

The AVDD pin also requires a bypass capacitor to GND. This LDO is for DRV8884 internal use only.

DRV8884 LDO_V_reg_lvsd39.gifFigure 22. LDO Diagram

If a digital input needs to be tied permanently high (that is, Mx, DECAY, or TRQ), it is preferable to tie the input to DVDD instead of an external regulator. This saves power when VM is not applied or in sleep mode; DVDD is disabled and current will not be flowing through the input pulldown resistors. For reference, logic level inputs have a typical pulldown of 100 kΩ, and tri-level inputs have a typical pulldown of 60 kΩ.