SNLS338F January   2011  – November 2014 DS100BR111


  1. Features
  2. Applications
  3. Description
  4. Simplified Schematic
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Electrical Characteristics
    5. 7.5 Electrical Characteristics — Serial Management Bus Interface
    6. 7.6 Timing Requirements — LOS and ENABLE / DISABLE Timing
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 4-Level Control Pin Settings
    4. 8.4 Device Functional Modes
      1. 8.4.1 Pin Control Mode
      2. 8.4.2 SMBus Slave Mode
      3. 8.4.3 SMBus Master Mode
      4. 8.4.4 Signal Conditioning Settings
    5. 8.5 Programming
      1. 8.5.1 System Management Bus (SMBus) and Configuration Registers
      2. 8.5.2 Transfer Of Data Via the SMBus
      3. 8.5.3 SMBus Transactions
      4. 8.5.4 Writing a Register
      5. 8.5.5 Reading a Register
      6. 8.5.6 EEPROM Programming
        1. Master EEPROM Programming
        2. EEPROM Address Mapping
    6. 8.6 Register Maps
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Signal Integrity in 10G-KR Applications
      2. 9.1.2 OOB (Out-of-Band) Functionality in SAS/SATA Applications
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Performance Plots
        1. Equalization Results (Pre-Channel Only)
        2. Equalization and De-Emphasis Results (Pre-channel and Post-channel, No Tx Source De-emphasis)
        3. Equalization and De-Emphasis Results (Pre-channel and Post-channel, -6 dB Tx Source De-emphasis)
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Bypass
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information



11 Layout

11.1 Layout Guidelines

The differential inputs and outputs are designed with 100 Ω differential terminations. Therefore, they should be connected to interconnects with controlled differential impedance of approximately 85-110 Ω. It is preferable to route differential lines primarily on one layer of the board, particularly for the input traces. The use of vias should be avoided if possible. If vias must be used, they should be used sparingly and must be placed symmetrically for each side of a given differential pair. Whenever differential vias are used, the layout must also provide for a low inductance path for the return currents as well. Route the differential signals away from other signals and noise sources on the printed circuit board. To minimize the effects of crosstalk, a 5:1 ratio or greater should be maintained between inter-pair spacing and trace width. See AN-1187 “Leadless Leadframe Package (LLP) Application Report” (literature number SNOA401) for additional information on QFN (WQFN) packages.

The DS100BR111 pinout promotes easy high speed routing and layout. To optimize DS100BR111 performance, refer to the following guidelines:

  1. Place local VIN and VDD capacitors as close as possible to the device supply pins. Often the best location is directly under the DS100BR111 pins to reduce the inductance path to the capacitor. In addition, bypass capacitors may share a via with the DAP GND to minimize ground loop inductance.
  2. Differential pairs going into or out of the DS100BR111 should have adequate pair-to-pair spacing to minimize crosstalk.
  3. Use return current via connections to link reference planes locally. This ensures a low inductance return current path when the differential signal changes layers.
  4. Optimize the via structure to minimize trace impedance mismatch.
  5. Place GND vias around the DAP perimeter to ensure optimal electrical and thermal performance. A 2x2 or 3x3 array of GND vias for the DAP is recommended.
  6. Use small body size AC coupling capacitors when possible — 0402 or smaller size is preferred. The AC coupling capacitors should be placed closer to the Rx on the channel.

11.2 Layout Example

In most cases, DS100BR111 layouts will fit neatly into a 1-lane application. The example layout in Figure 40 shows the DS100BR111 channels in a typical 1-lane bidirectional layout.

ds100br111layout.gifFigure 40. DS100BR111 Example Layout