SNLS338F January   2011  – November 2014 DS100BR111

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Electrical Characteristics
    5. 7.5 Electrical Characteristics — Serial Management Bus Interface
    6. 7.6 Timing Requirements — LOS and ENABLE / DISABLE Timing
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 4-Level Control Pin Settings
    4. 8.4 Device Functional Modes
      1. 8.4.1 Pin Control Mode
      2. 8.4.2 SMBus Slave Mode
      3. 8.4.3 SMBus Master Mode
      4. 8.4.4 Signal Conditioning Settings
    5. 8.5 Programming
      1. 8.5.1 System Management Bus (SMBus) and Configuration Registers
      2. 8.5.2 Transfer Of Data Via the SMBus
      3. 8.5.3 SMBus Transactions
      4. 8.5.4 Writing a Register
      5. 8.5.5 Reading a Register
      6. 8.5.6 EEPROM Programming
        1. 8.5.6.1 Master EEPROM Programming
        2. 8.5.6.2 EEPROM Address Mapping
    6. 8.6 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Signal Integrity in 10G-KR Applications
      2. 9.1.2 OOB (Out-of-Band) Functionality in SAS/SATA Applications
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Performance Plots
        1. 9.2.3.1 Equalization Results (Pre-Channel Only)
        2. 9.2.3.2 Equalization and De-Emphasis Results (Pre-channel and Post-channel, No Tx Source De-emphasis)
        3. 9.2.3.3 Equalization and De-Emphasis Results (Pre-channel and Post-channel, -6 dB Tx Source De-emphasis)
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Bypass
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

24-Pin
RTW Package
Top View
30138825.gif
1. The center DAP on the package bottom is the device GND connection. This pad must be connected to GND through multiple (minimum of 4) vias to ensure optimal electrical and thermal performance.

Pin Functions(1)

PIN I/O, TYPE DESCRIPTION
NAME NUMBER
DIFFERENTIAL HIGH SPEED I/O's
INA+, INA- ,
INB+, INB-		 24, 23
11, 12		 I, CML Inverting and non-inverting CML differential inputs to the equalizer. On-chip 50 Ω termination resistors connect both INx+ and INx- to VDD. Compatible with AC coupled CML inputs.
OUTA+, OUTA-,
OUTB+, OUTB-		 7, 8
20, 19		 O, CML Inverting and non-inverting 50 Ω driver outputs with de-emphasis. Compatible with AC coupled CML inputs.
CONTROL PINS
ENSMB 3 I, 4-LEVEL,
LVCMOS		 System Management Bus (SMBus) Enable Pin
High = Register Access SMBus Slave Mode
Float = Read External EEPROM (SMBus Master Mode)
Tie 1 kΩ to GND = Pin Mode
ENSMB = Float or 1 (SMBus MODES)
SCL 5 I, 2-LEVEL,
LVCMOS,
O, Open Drain		 Clock output when loading EEPROM configuration, reverting to SMBus clock input when EEPROM load is complete (ALL_DONE = 0).
External 2 kΩ to 5 kΩ pull-up resistor to VDD (2.5 V mode) or VIN (3.3 V mode) recommended as per SMBus interface standards(2)
SDA 4 I, 2-LEVEL,
LVCMOS,
O, Open Drain		 In both SMBus Modes, this pin is the SMBus data I/O. Data input or open drain output.
External 2 kΩ to 5 kΩ pull-up resistor to VDD (2.5 V mode) or VIN (3.3 V mode) recommended as per SMBus interface standards(2)
AD0-AD3 10, 9, 2, 1 I, 4-LEVEL,
LVCMOS		 ENSMB Master or Slave mode
SMBus Slave Address Inputs. In SMBus mode, these pins are the user set SMBus slave address inputs. There are 16 addresses supported by these pins.
Pins must be tied Low or High when used to define the device SMBus address. (4)
READEN 17 I, 2-LEVEL,
LVCMOS		 ENSMB = Float: When using SMBus Master Mode, a logic low on this pin starts the load from the external EEPROM.
ENSMB = 1: When using SMBus Slave Mode, the VOD_SEL/READEN pin must be tied Low for the AD[3:0] to be active. If this pin is tied High or left floating, an address of 0xB0 will be used for the DS100BR111.
DONE 18 O, 2-LEVEL,
LVCMOS		 When using an External EEPROM (ENSMB = Float), Valid Register Load Status Output
High = External EEPROM load failed or incomplete
Low = External EEPROM load passed
ENSMB = 0 (PIN MODE)
EQA0, EQA1
EQB0, EQB1		 10, 9
1, 2		 I, 4-LEVEL,
LVCMOS 		EQA[1:0] and EQB[1:0] control the level of equalization on the input pins. EQA[1:0] controls the A channel, and EQB[1:0] controls the B channel. The pins are only active when ENSMB = 0.
When ENSMB = 1, the SMBus registers provide independent control of each channel, and the EQB0/B1 pins are converted to SMBus AD2/AD3 inputs.
See Table 3 for additional information.
DEMA, DEMB 4, 5 I, 4-LEVEL,
LVCMOS 		DEMA and DEMB control the level of de-emphasis for the output driver when in 10G mode. DEMA controls the A channel, and DEMB controls the B channel. The pins are only active when ENSMB = 0.
When ENSMB = 1, the SMBus registers provide independent control of each channel, and the DEM pins are converted to SMBus SCL and SDA pins.
See Table 4 for additional information.
VOD_SEL 17 I, 4-LEVEL,
LVCMOS 		VOD Select
High = 10G-KR Mode (VOD = 1.1 Vpp or 1.3 Vpp)
Float = (VOD = 1.0 Vpp)
20 kΩ to GND = (VOD = 1.2 Vpp)
1 kΩ to GND = (VOD = 700 mVpp)
See (4)(5) for additional notes. See Table 2 for additional information.
MODE 18 I, 4-LEVEL,
LVCMOS 		Controls Device Mode of Operation
High= 10GbE Mode, Continuous Talk (Output Always On)
Float = 10G-KR Mode, Slow OOB
20 kΩ to GND = eSATA Mode, Fast OOB, Auto Low Power on 100 µs of inactivity. SD stays active.
1 kΩ to GND = SAS Mode, Fast OOB
CONTROL PINS — BOTH PIN AND SMBus MODES (LVCMOS)
TX_DIS 6 I, 2-LEVEL,
LVCMOS		 High = OUTA Enabled, OUTB Disabled
Low = OUTA and OUTB Enabled
LOS 13 O, Open Drain Indicates Loss of Signal (Default is LOS on INA). Can be modified via SMBus registers.
SD_TH 14 I, 4-LEVEL,
LVCMOS		 The SD_TH pin controls LOS threshold setting
Assert (mVpp), Deassert (mVpp)
High = 190 mVpp, 130 mVpp
Float = 180 mVpp, 110 mVpp (Default)
20 kΩ to GND = 160 mVpp, 100 mVpp
1 kΩ to GND = 210 mVpp, 150 mVpp(3)
VDD_SEL 16 I, FLOAT Enables the 3.3 V to 2.5 V internal regulator
Low = 3.3 V Operation
Float = 2.5 V Operation
POWER
VDD 21, 22 Power Power supply pins
When in 2.5 V mode, connect to 2.5 V supply.
When in 3.3 V mode, do not connect to any supply voltage. Should be used to attach external decoupling to device, 100 nF recommended.
See Power Supply Recommendations for additional information.
VIN 15 Power VIN = 3.3 V ± 10% (input to internal LDO regulator)
When in 2.5 V mode, VIN pin must be left floating.
See Power Supply Recommendations for additional information.
GND DAP Power Ground pad (DAP - die attach pad).
(1) LVCMOS inputs without the “Float” conditions must be driven to a logic low or high at all times or operation is not ensured. Unless the "Float" level is desired, 4-Level input pins require a minimum 1 kΩ resistor to GND, VDD (in 2.5 V mode), or VIN (in 3.3 V mode). Input edge rate for LVCMOS/FLOAT inputs must be faster than 50 ns from 10–90%.
(2) SCL and SDA pins can be tied either to 3.3 V or 2.5 V, regardless of whether the device is operating in 2.5 V mode or 3.3 V mode.
(3) Using values less than the default level can extend the time required to detect LOS and are not recommended.
(4) Setting VOD_SEL = High in SMBus Mode will force the SMBus Address = 0xB0
(5) DS100BR111 OUTA is limited to 700 mVpp in pin mode.