SNLS448A January   2013  – October 2015 DS100RT410

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Device Data Path Operation
      2. 7.3.2  Signal Detect
      3. 7.3.3  CTLE
      4. 7.3.4  Clock and Data Recovery
      5. 7.3.5  Output Driver
      6. 7.3.6  CTLE Boost Setting
      7. 7.3.7  Driver Output Voltage
      8. 7.3.8  Driver Output De-Emphasis
      9. 7.3.9  Driver Output Rise and Fall Time
      10. 7.3.10 Ref_mode 0 Mode (Reference Clock Not Required)
      11. 7.3.11 Ref_mode 3 Mode (Reference Clock Required)
      12. 7.3.12 False Lock Detector Setting
      13. 7.3.13 Reference Clock In
      14. 7.3.14 Reference Clock Out
      15. 7.3.15 Daisy Chain of REFCLK_OUT to REFCLK_IN
      16. 7.3.16 INT
      17. 7.3.17 LOCK_3, LOCK_2, LOCK_1, and LOCK_0
    4. 7.4 Device Functional Modes
      1. 7.4.1 SMBus Master Mode and SMBus Slave Mode
      2. 7.4.2 Address Lines <ADDR_[3:0]>
      3. 7.4.3 SDA and SDC
    5. 7.5 Programming
      1. 7.5.1  SMBus Strap Observation
      2. 7.5.2  Device Revision and Device ID
      3. 7.5.3  Control/Shared Register Reset
      4. 7.5.4  Interrupt Channel Flag Bits
      5. 7.5.5  SMBus Master Mode Control Bits
      6. 7.5.6  Resetting Individual Channels of the Retimer
      7. 7.5.7  Interrupt Status
      8. 7.5.8  Overriding the CTLE Boost Setting
      9. 7.5.9  Overriding the VCO CAP DAC Values
      10. 7.5.10 Overriding the Output Multiplexer
      11. 7.5.11 Overriding the VCO Divider Selection
      12. 7.5.12 Using the PRBS Generator
      13. 7.5.13 Using the Internal Eye Opening Monitor
      14. 7.5.14 Enabling Slow Rise and Fall Time on the Output Driver
      15. 7.5.15 Inverting the Output Polarity
      16. 7.5.16 Overriding the Figure of Merit for Adaptation
      17. 7.5.17 Setting the Rate and Subrate for Lock Acquisition
      18. 7.5.18 Setting the Adaptation/Lock Mode
      19. 7.5.19 Initiating Adaptation
      20. 7.5.20 Setting the Reference Enable Mode
      21. 7.5.21 Overriding the CTLE Settings Used for CTLE Adaptation
      22. 7.5.22 Setting the Output Differential Voltage
      23. 7.5.23 Setting the Output De-emphasis Setting
    6. 7.6 Register Maps
      1. 7.6.1 Register Information
      2. 7.6.2 Bit Fields in the Register Set
      3. 7.6.3 Writing to and Reading from the Control/Shared Registers
      4. 7.6.4 Channel Select Register
      5. 7.6.5 Reading to and Writing from the Channel Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9 Power Supply Recommendations

Figure 9 depicts an example power connections diagram for the DS100RT410. The supply (VDD) and ground (GND) Pins should be connected to power planes routed on adjacent layers of the printed circuit board. The layer thickness of the dielectric should be minimized so that the VDD and GND planes create a low inductance supply with distributed capacitance. Second, careful attention to supply bypassing through the proper use of bypass capacitors is required. A 0.1-μF bypass capacitor should be connected to each VDD Pin such that the capacitor is placed as close as possible to the DS100RT410. Smaller body size capacitors can help facilitate proper component placement. Additionally, capacitor with capacitance in the range of 1 μF to 10 μF should be incorporated in the power supply bypassing design as well. These capacitors can be either tantalum or an ultra-low ESR ceramic.

DS100RT410 SNLS399_DF410_power_supply_rec_snls399.gif Figure 9. Example Power Connection