JAJSBK7H January   2012  – February 2018 DS125DF410

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     代表的なアプリケーションの図
  4. 改訂履歴
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Data Path Operation
      2. 7.3.2 Signal Detect
      3. 7.3.3 CTLE
      4. 7.3.4 DFE
      5. 7.3.5 Clock and Data Recovery
      6. 7.3.6 Output Driver
      7. 7.3.7 Device Configuration
        1. 7.3.7.1 Rate and Subrate Setting
    4. 7.4 Device Functional Modes
      1. 7.4.1 SMBus Master Mode and SMBus Slave Mode
      2. 7.4.2 Address Lines <ADDR_[3:0]>
      3. 7.4.3 SDA and SDC
      4. 7.4.4 Standards-Based Modes
        1. 7.4.4.1 Ref_mode 3 Mode (Reference Clock Required)
        2. 7.4.4.2 False Lock Detector Setting
        3. 7.4.4.3 Reference Clock In
        4. 7.4.4.4 Reference Clock Out
        5. 7.4.4.5 Driver Output Voltage
        6. 7.4.4.6 Driver Output De-Emphasis
        7. 7.4.4.7 Driver Output Rise/Fall Time
        8. 7.4.4.8 INT
        9. 7.4.4.9 LOCK_3, LOCK_2, LOCK_1, and LOCK_0
    5. 7.5 Programming
      1. 7.5.1  SMBus Strap Observation
      2. 7.5.2  Device Revision and Device ID
      3. 7.5.3  Control/Shared Register Reset
      4. 7.5.4  Interrupt Channel Flag Bits
      5. 7.5.5  SMBus Master Mode Control Bits
      6. 7.5.6  Resetting Individual Channels of the Retimer
      7. 7.5.7  Interrupt Status
      8. 7.5.8  Overriding the CTLE Boost Setting
      9. 7.5.9  Overriding the VCO Search Values
      10. 7.5.10 Overriding the Output Multiplexer
      11. 7.5.11 Overriding the VCO Divider Selection
      12. 7.5.12 Using the PRBS Generator
      13. 7.5.13 Using the Internal Eye Opening Monitor
      14. 7.5.14 Overriding the DFE Tap Weights and Polarities
      15. 7.5.15 Enabling Slow Rise/Fall Time on the Output Driver
      16. 7.5.16 Inverting the Output Polarity
      17. 7.5.17 Overriding the Figure of Merit for Adaptation
      18. 7.5.18 Setting the Rate and Subrate for Lock Acquisition
      19. 7.5.19 Setting the Adaptation/Lock Mode
      20. 7.5.20 Initiating Adaptation
      21. 7.5.21 Setting the Reference Enable Mode
      22. 7.5.22 Overriding the CTLE Settings Used for CTLE Adaptation
      23. 7.5.23 Setting the Output Differential Voltage
      24. 7.5.24 Setting the Output De-Emphasis Setting
    6. 7.6 Register Maps
      1. 7.6.1 Register Information
      2. 7.6.2 Bit Fields in the Register Set
      3. 7.6.3 Writing to and Reading from the Control/Shared Registers
      4. 7.6.4 Channel Select Register
      5. 7.6.5 Reading to and Writing from the Channel Registers
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 商標
    3. 11.3 静電気放電に関する注意事項
    4. 11.4 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Electrical Characteristics

over recommended operating supply and temperature ranges with default register settings unless otherwise specified(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER
PD Power Supply Consumption Average power consumption (DFE powered-up and enabled)(2) 720 mW
Max transient power supply current(3) 500 610 mA
NTPS Supply Noise Tolerance(4) 50 Hz to 100 Hz 100 mVP-P
100 Hz to 10 MHz 40 mVP-P
10 MHz to 5.0 GHz 10 mVP-P
2.5V LVCMOS DC SPECIFICATIONS
VIH High Level Input Voltage 1.75 VDD V
High Level (ADDR[3:0] pins) 2.28 VDD
VIL Low Level Input Voltage GND 0.7 V
Low Level Input Voltage (ADDR[3:0] pins) GND 0.335
VOH High Level Output Voltage IOH = -3 mA 2.0 V
VOL Low Level Output Voltage IOL = 3 mA 0.4 V
IIN Input Leakage Current VIN = VDD 10 μA
VIN = GND –10 μA
IIH Input High Current (EN_SMB pin) VIN = VDD +55 μA
IIL Input Low Current (EN_SMB pin) VIN = GND -110 μA
3.3 V LVCMOS DC SPECIFICATIONS (SDA, SDC, INT)
VIH High Level Input Voltage VDD = 2.5 V 1.75 3.6 V
VIL Low Level Input Voltage VDD = 2.5 V GND 0.7 V
VOL Low Level Output Voltage IPULLUP = 3 mA 0.4 V
IIH Input High Current VIN = 3.6 V, VDD = 2.5 V 20 40 μA
IIL Input Low Current VIN = GND, VDD = 2.5 V –10 10 μA
fSDC SMBus clock rate Slave Mode 100 400 kHz
Master Mode(5) 400 kHz
DATA BIT RATES
RB Bit Rate Range 9.8 12.5 Gbps
SIGNAL DETECT
SDH Signal Detect ON Threshold Level Default input signal level to assert signal detect,
10.3125 Gbps, PRBS-31
70 mVp-p
SDL Signal Detect OFF Threshold Level Default input signal level to de-assert signal detect, 10.3125 Gbps, PRBS-31 10 mVp-p
RECEIVER INPUTS (RXPn, RXNn)
VTX2, min Minimum Source Transmit Launch Signal Level (IN, diff) See (6) 600 mVP-P
VTX2, max 1000 mVP-P
VTX1, max See (7) 1200 mVP-P
VTX0, max See (8) 1600 mVP-P
LRI Maximum Differential Input Return Loss - |SDD11| 100 MHz – 6 GHz –15 dB
ZD Differential Input Impedance 100 MHz – 6 GHz 100
ZS Single-Ended Input Impedance 100 MHz – 6 GHz 50
DRIVER OUTPUTS (TXPn, TXNn)
VOD0 Differential output voltage Differential measurement with OUT+ and OUT- terminated by 50 Ω to GND, AC-Coupled,
SMBus register VOD control (Register 0x2d bits 2:0) set to 0, minimum VOD
De-emphasis control set to minimum (0 dB)
400 675 mVP-P
VOD7 Differential output voltage Differential measurement with OUT+ and OUT- terminated by 50 Ω to GND, AC-Coupled
SMBus register VOD control (Register 0x2d bits 2:0) set to 7, maximum VOD
De-emphasis control set to minimum (0 dB)
1000 mVP-P
VOD_DE De-emphasis level(10) Differential measurement with OUT+ and OUT- terminated by 50 Ω to GND, AC-Coupled
Set by SMBus register control to maximum de-emphasis setting
Relative to the nominal 0 dB de-emphasis level set at the minimum de-emphasis setting
–15 dB
tR, tF Transition time (rise and fall times)(10)(11) Transition time control = Full Slew Rate 39 ps
Transition time control = Limited Slew Rate 50 ps
LRO Maximum Differential Output Return Loss - |SDD22| 100 MHz – 6 GHz(9) –15 dB
tDP Propagation Delay Retimed data 300 ps
TDE De-emphasis pulse duration(12) Measured at VOD = 1000 mVP-P,
de-emphasis setting = -12 dB
75 ps
TJ Output total jitter Measured at BER = 10-12(13) 10 ps
TSKEW Intra Pair Skew Difference in 50% crossing between TXPn and TXNn for any output 3 ps
Channel-to-Channel Skew 7 ps
CLOCK AND DATA RECOVERY
BWPLL PLL Bandwidth, -3 dB Measured at 10.3125 Gbps 5 MHz
JTOL Input sinusoidal jitter tolerance
10 kHz to 250 MHz sinusoidal jitter frequency
Measured at BER = 10-15 0.6 UI
JTRANS Jitter Transfer Sinusoidal jitter at 10 MHz jitter frequency Measured at BER = 10-15 –6 dB
TLOCK CDR Lock Time, Ref_mode 3,
Fixed Data Rate (eg. 10.3125 Gbps)
Fixed (manual setting) of CTLE, DFE HEO/VEO lock monitor disabled (register 0x3e, bit 7 set to 0) 2 ms
Fixed (manual setting) of CTLE, DFE HEO/VEO lock monitor enabled (register 0x3e, bit 7 set to 1 - default) 12 ms
Medium (20 inch) channel loss with CTLE and DFE adaption, HEO/VEO lock monitor must be enabled (14) 74 ms
TEMPLOCK CDR Lock, Ref_mode 3, 12.5Gbps Parameter tested within -40°C to +85°C ambient range 100 °C
RECOMMENDED REFERENCE CLOCK SPECIFICATIONS
REFf Input reference clock frequency 24.9975 25 25.0025 MHz
REFCLK_INPW Minimum REFCLK_IN Pulse Width At REFCLK_IN pin 4 ns
REFCLK_OUTDCD REFCLK_OUT duty cycle distortion CL = 5 pF 0.55 ns
REFVIH Reference clock input min high threshold 1.75 V
REFVIL Reference clock input max low threshold 0.7 V
Typical values represent most likely parametric norms at VDD = 2.5V, TA = 25°C., and at the Recommended Operation Conditions at the time of product characterization.
VDD= 2.5V, TA = 25°C. All four channels active and locked. DFE is powered-up and enabled.
Max momentary power supply current lasting less than 1s. The retimer may consume more power than the maximum average power rating during the time required to acquire CDR lock.
Allowed supply noise (mVP-P sine wave) under typical conditions.
EEPROM device used for Master mode programming must support fSDC greater than 400kHz.
Differential signal amplitude at the transmitter output providing < 1x10-12 bit error rate. Measured at 10.3125 Gbps with a PRBS-31 data pattern. Input transmission channel is 40-inch long FR-4 stripline, 4-mil trace width.
Differential signal amplitude at the transmitter output providing < 1x10-12 bit error rate. Measured at 10.3125 Gbps with a PRBS-31 data pattern. Input transmission channel is 30-inch long FR-4 stripline, 4-mil trace width.
Differential signal amplitude at the transmitter output providing < 1x10-12 bit error rate. Measured at 10.3125 Gbps with a PRBS-31 data pattern. No input transmission channel.
Measured with 10 MHz clock pattern output.
Measured with clock-like \{11111 00000\} pattern.
Slew rate is controlled by SMBus register settings.
De-emphasis pulse width varies with VOD and de-emphasis settings.
Typical with no output de-emphasis, minimum output transmission channel.
The CDR lock time is when the input has a valid signal to when the output sends retimed data. The CDR lock time is after the CTLE adaption is completed. In adapt_mode 2 or 3, the DFE adaption will continue after the CDR lock time.