JAJSBK7H January 2012 – February 2018 DS125DF410
Register 0x2c, bits 3:0, Register 0x2f, bit 3, Register 0x39, bits 4:0, and Registers 0x50-0x5f
The CTLE adaptation algorithm operates by setting the CTLE boost stage controls to a set of pre-determined boost settings, each of which provides progressively more high-frequency boost. At each stage in the adaptation process, the DS125DF410 attempts to phase lock to the equalized signal. If the phase lock succeeds, the DS125DF410 measures the horizontal and vertical eye openings using the internal eye monitor circuit. The DS125DF410 computes a figure of merit for the eye opening and compares it to the previous best value of the figure of merit. While the figure of merit continues to improve, the DS125DF410 continues to try additional values of the CTLE boost setting until the figure of merit ceases to improve and begins to degrade. When the figure of merit starts to degrade, the DS125DF410 still continues to try additional CTLE settings for a pre-determined trial count called the “look-beyond” count, and if no improvement in the figure of merit results, it resets the CTLE boost values to those that produced the best figure of merit. The resulting CTLE boost values are then stored in register 0x03. The “look-beyond” count is configured by the value in register 0x2c, bits 3:0. The value is 0x2 by default.
The set of boost values used as candidate values during CTLE adaptation are stored as bit fields in registers 0x40-0x5f. The default values for these settings are shown in Table 11. These values may be overridden by setting the corresponding register values over the SMBus. If these values are overridden, then the next time the CTLE adaptation is performed the set of CTLE boost values stored in these registers will be used for the adaptation. Resetting the channel registers by setting bit 2 of channel register 0x00 will reset the CTLE boost settings to their defaults. So will power-cycling the DS125DF410.
|Register (Hex)||Bits 7:6 (CTLE Stage 0)||Bits 5:4 (CTLE Stage 1)||Bits 3:2 (CTLE Stage 2)||Bits 1:0 (CTLE Stage 3)||CTLE Boost String||CTLE Adaptation Index|
As an alternative to, or in conjunction with, writing the CTLE boost setting registers 0x40 through 0x5f, it is possible to set the starting CTLE boost setting index. To override the default setting, which is 0, set bit 3 of register 0x2f. When this bit is set, the starting index for adaptation comes from register 0x39, bits 4:0. This is the index into the CTLE settings table in registers 0x40 through 0x5f. When this starting index is 0, which is the default, CTLE adaptation starts at the first setting in the table, the one in register 0x40, and continues until the optimum FOM is reached.