JAJSBK7H January 2012 – February 2018 DS125DF410
The CML inputs and outputs have been optimized to work with interconnects using a controlled differential impedance of 100 Ω. It is preferable to route differential lines exclusively on one layer of the board, particularly for the input traces. The use of vias should be avoided if possible. If vias must be used, they should be used sparingly and must be placed symmetrically for each side of a given differential pair. Whenever differential vias are used the layout must also provide for a low inductance path for the return currents as well. Route the differential signals away from other signals and noise sources on the printed circuit board. See AN-1187 Leadless Leadframe Package (LLP) Application Report (SNOA401) for additional information on QFN (WQFN) packages.