The Analog Subsystem has ADC1, ADC2, and six Analog Comparator + DAC units that can be accessed through the Analog Common Interface Bus. The ADC Result Registers are accessible by CPUs and DMAs of the Master and Control Subsystems. All other Analog Peripheral Registers are accessible by the C28x CPU only. The C28x CPU accesses the ACIB through the C28x Memory Bus, and the C28x DMA through the C28x DMA Bus. The ACIB arbitrates for access to ADC and Analog Comparator registers between CPU/DMA bus cycles of the C28x Subsystem with those of the Cortex-M3 Subsystem. In addition to managing bus cycles, the ACIB also transfers Start-Of-Conversion triggers to the Analog Subsystem and returns End-Of-Conversion ADC interrupts to both the Master Subsystem and the Control Subsystem.
There are 22 possible Start-Of-Conversion (SOC) sources from the C28x Subsystem that are mapped to a total of 8 possible SOC triggers inside the Analog Subsystem (to ADC1 and ADC2).
Going the other way, eight End-Of-Conversion (EOC) sources from ADC1 and eight EOC sources from ADC2 are AND-ed together to form eight interrupts going to destinations in both the Master and Control Subsystems. Inside the C28x Subsystem, all eight EOC interrupts go to the PIE, but only four of the same eight go to the C28x DMA.
The Concerto MCU Analog Subsystem has two independent Analog-to-Digital Converters (ADC1, ADC2); six Analog Comparators + DAC units; and an ACIB to facilitate analog data communications with the two digital subsystems of Concerto (Cortex-M3 and C28x).
Figure 6-3 shows the Analog Subsystem.