This device provides one high-speed McBSP that allows direct interface to codecs and other devices. The CPU accesses data, control, and status information. The MCBSP also supports µDMA transfers.
The McBSP consists of a data-flow path and a control path connected to external devices by six pins. Data is communicated to devices interfaced with the McBSP through the data transmit (DX) pin for transmission and through the data receive (DR) pin for reception. Control information in the form of clocking and frame synchronization is communicated through the following pins: CLKX (transmit clock), CLKR (receive clock), FSX (transmit frame synchronization), and FSR (receive frame synchronization).
The CPU and the DMA controller communicate with the McBSP through 16-bit-wide registers accessible through the internal peripheral bus. The CPU or the DMA controller writes the data to be transmitted to the data transmit registers (DXR1, DXR2). Data written to the DXRs is shifted out to DX through the transmit shift registers (XSR1, XSR2). Similarly, receive data on the DR pin is shifted into the receive shift registers (RSR1, RSR2) and copied into the receive buffer registers (RBR1, RBR2). The contents of the RBRs is then copied to the DRRs, which can be read by the CPU or the DMA controller. This method allows simultaneous movement of internal and external data communications.
DRR2, RBR2, RSR2, DXR2, and XSR2 are not used (written, read, or shifted) if the serial word length is 8 bits, 12 bits, or 16 bits. For larger word lengths, these registers are needed to hold the most significant bits.
The frame and clock loop-back is implemented at chip level to enable CLKX and FSX to drive CLKR and FSR. If the loop-back is enabled, the CLKR and FSR get their signals from the CLKX and FSX pads instead of the CLKR and FSR pins.
McBSP features include:
A value of the chosen data size is referred to as a serial word or word in this section. Elsewhere, word is used to describe a 16-bit value.
Figure 5-55 shows the C28x McBSP peripheral.