The CLKIN input clock to the C28x processor is normally a divided-down output of the Main PLL or X1 external clock input. There are four registers associated with the Main PLL: SYSPLLCTL, SYSPLLMULT, SYSPLLSTAT and SYSDIVSEL. Typically, the Cortex-M3 processor writes to these registers, while the C28x processor has read access. The C28x can request write access to the above registers through the CLKREQEST register. The Cortex-M3 can regain write ownership of these registers through the MCLKREQUEST register.
Individual C28x peripherals can be turned on or off by gating C28SYSCLK to those peripherals, which is done through the CPCLKCR0,2,3 registers.
The C28x processor outputs two clocks: C28CPUCLK and C28SYSCLK. The C28SYSCLK is used by C28x peripherals, C28x Timer 0, C28x Timer 1, and C28x Timer 2. C28x Timer 2 can also be clocked by OSCCLK or 10MHZCLK (see Figure 6-12). The C28CPUCLK is used by the C28x CPU, FPU, VCU, and PIE.
The Control Subsystem operates in one of three modes: Normal Mode, IDLE Mode, or STANDBY Mode. Table 6-26 shows the Control Subsystem low-power modes and their effect on the C28x CPU, clocks, and peripherals. Figure 6-12 shows the Control Subsystem clocks and low-power modes.
|STATE OF C28x CPU||C28CPUCLK(2)||C28SYSCLK(3)||REGISTERS USED TO GATE CLOCKS TO