Each I2C module comprises both master and slave functions. For proper operation, the SDA and SCL pins must be configured as open-drain signals.
The I2C bus uses only two signals: SDA and SCL, named I2CSDA and I2CSCL. SDA is the bidirectional serial data line and SCL is the bidirectional serial clock line. The bus is considered idle when both lines are high.
Every transaction on the I2C bus is 9 bits long, consisting of eight data bits and a single acknowledge bit. The number of bytes per transfer (defined as the time between a valid START and STOP condition) is unrestricted, but each byte has to be followed by an acknowledge bit, and data must be transferred MSB first. When a receiver cannot receive another complete byte, the receiver can hold the clock line SCL Low and force the transmitter into a wait state. The data transfer continues when the receiver releases the clock SCL.