Most Concerto external pins are shared among many internal peripherals. This sharing of pins is accomplished through several I/O muxes where a specific physical pin can be assigned to selected signals of internal peripherals.
Most of the I/O pins of the Concerto MCU can also be configured as programmable GPIOs. Exceptions include the X1 and X2 oscillator inputs; the XRS digital reset and ARS analog reset; the VREG12EN and VREG18EN internal voltage regulator enables; and five JTAG pins. The 144 primary GPIOs are grouped in 2 programmable blocks: GPIO_MUX1 block (136 pins) and GPIO_MUX2 block (8 pins). Additionally, eight secondary GPIOs are available through the AIO_MUX1 block (four pins) and AIO_MUX2 block (four pins). Figure 6-14 shows the GPIOs and other pins.