The internal PLLSYSCLK clock, normally used as a source for all Master Subsystem clocks, is a divided-down output of the Main PLL or X1 external clock input, as defined by the SPLLCKEN bit of the SYSPLLCTL register.
There is also a second oscillator that internally generates two clocks: 32KHZCLK and 10MHZCLK. The 10MHZCLK is used by the Missing Clock Circuit to detect a possible absence of an external clock source to the Main Oscillator that drives the Main PLL. Detection of a missing clock results in a substitution of the 10MHZCLK for the PLLSYSCLK. The CLKFAIL signal is also sent to the NMI Block and the Control Subsystem where this signal can trip the ePWM peripherals.
The 32KHZCLK and 10MMHZCLK clocks are also used by the Cortex-M3 Subsystem as possible sources for the Deep Sleep Clock.
There are four registers associated with the Main PLL: SYSPLLCTL, SYSPLLMULT, SYSPLLSTAT and SYSDIVSEL. Typically, the Cortex-M3 processor writes to these registers, while the C28x processor has read access. The C28x can request write access to the above registers through the CLKREQEST register. Cortex-M3 can regain write ownership of these registers through the MCLKREQUEST register.
The Master Subsystem operates in one of three modes: Run Mode, Sleep Mode, or Deep Sleep Mode. Table 6-25 shows the Master Subsystem low-power modes and their effect on both CPUs, clocks, and peripherals. Figure 6-10 shows the Cortex-M3 clocks and the Master Subsystem low-power modes.
|REGISTER USED TO GATE CLOCKS TO Cortex-M3 PERIPHERALS||MAIN PLL||USB PLL||CLOCK TO C28x||CLOCK TO SHARED RESOURCES||CLOCK TO ANALOG SUBSYSTEM|
|Sleep||Stopped||M3SSCLK(1)||RCGC or SCGC(4)||On||On||PLLSYSCLK(2)||PLLSYSCLK(2)||ASYSCLK(3)|
|Deep Sleep||Stopped||M3DSDIVCLK(5)||RCGC or DCGC(4)||Off||Off||Off||Off||Off|
Figure 6-11 shows the system clock/PLL.