There is no power sequencing requirement needed to ensure the device is in the proper state after reset or to prevent the I/Os from glitching during power up and power down. (All I/Os, except for GPIO199, are glitch-free during power up and power down.) No voltage larger than a diode drop (0.7 V) above VDDIO should be applied to any digital pin (for analog pins, this value is 0.7 V above VDDA) before powering up the device. Voltages applied to pins on an unpowered device can bias internal p-n junctions in unintended ways and produce unpredictable results.
A. Upon power up, PLLSYSCLK is OSCCLK/8. Because the XCLKOUTDIV bits in the XCLK register come up with a reset state of 0, PLLSYSCLK is further divided by 4 before PLLSYSCLK appears at XCLKOUT. XCLKOUT = OSCCLK/32 during this phase.
B. Boot ROM configures the SYSDIVSEL bits for /1 operation. XCLKOUT = OSCCLK/4 during this phase. XCLKOUT will not be visible at the pin until explicitly configured by user code.
C. After reset, the boot ROM code samples Boot Mode pins. Based on the status of the Boot Mode pin, the boot code branches to destination memory or boot code function. If boot ROM code executes after power-on conditions (in debugger environment), the boot code execution time is based on the current M3SSCLK speed. The M3SSCLK will be based on user environment and could be with or without PLL enabled.
D. The XRS pin will be driven low by on-chip POR circuitry until the VDDIO voltage crosses the POR threshold. (The POR threshold is lower than the operating voltage requirement.) To allow the external clock to stabilize, the XRS pin may also need to be driven low by the system for additional time.Figure 5-1 Power-On Reset