This device has four SSI modules. Each SSI has a Master or Slave interface for synchronous serial communication with peripheral devices that have Texas Instruments™ SSIs, SPI, or Freescale™ serial format.
The SSI peripheral performs serial-to-parallel conversion on data received from a peripheral device. The CPU accesses data, control, and status information. The transmit and receive paths are buffered with internal FIFO memories, allowing up to eight 16-bit values to be stored independently in both transmit and receive modes. The SSI also supports µDMA transfers. The transmit and receive FIFOs can be programmed as destination/source addresses in the µDMA module. An µDMA operation is enabled by setting the appropriate bit or bits in the SSIDMACTL register.
Figure 5-30 shows the SSI peripheral.