SBOS547A June 2011 – August 2015 INA226
The INA226 is a digital current sense amplifier with an I2C- and SMBus-compatible interface. It provides digital current, voltage, and power readings necessary for accurate decision-making in precisely-controlled systems. Programmable registers allow flexible configuration for measurement resolution as well as continuous-versus-triggered operation. Detailed register information appears at the end of this data sheet, beginning with Table 4. See the Functional Block Diagram section for a block diagram of the INA226 device.
The INA226 device performs two measurements on the power-supply bus of interest. The voltage developed from the load current that flows through a shunt resistor creates a shunt voltage that is measured at the IN+ and IN– pins. The device can also measure the power supply bus voltage by connecting this voltage to the VBUS pin. The differential shunt voltage is measured with respect to the IN– pin while the bus voltage is measured with respect to ground.
The device is typically powered by a separate supply that can range from 2.7 V to 5.5 V. The bus that is being monitored can range in voltage from 0 V to 36 V. Based on the fixed 1.25-mV LSB for the Bus Voltage Register that a full-scale register results in a 40.96 V value.
Do not apply more than 36 V of actual voltage to the input pins.
There are no special considerations for power-supply sequencing because the common-mode input range and power-supply voltage are independent of each other; therefore, the bus voltage can be present with the supply voltage off, and vice-versa.
The device takes two measurements, shunt voltage and bus voltage. It then converts these measurements to current, based on the Calibration Register value, and then calculates power. Refer to the Programming the Calibration Register section for additional information on programming the Calibration Register.
The device has two operating modes, continuous and triggered, that determine how the ADC operates following these conversions. When the device is in the normal operating mode (that is, MODE bits of the Configuration Register (00h) are set to '111'), it continuously converts a shunt voltage reading followed by a bus voltage reading. After the shunt voltage reading, the current value is calculated (based on Equation 3). This current value is then used to calculate the power result (using Equation 4). These values are subsequently stored in an accumulator, and the measurement/calculation sequence repeats until the number of averages set in the Configuration Register (00h) is reached. Following every sequence, the present set of values measured and calculated are appended to previously collected values. After all of the averaging has been completed, the final values for shunt voltage, bus voltage, current, and power are updated in the corresponding registers that can then be read. These values remain in the data output registers until they are replaced by the next fully completed conversion results. Reading the data output registers does not affect a conversion in progress.
The mode control in the Conversion Register (00h) also permits selecting modes to convert only the shunt voltage or the bus voltage in order to further allow the user to configure the monitoring function to fit the specific application requirements.
All current and power calculations are performed in the background and do not contribute to conversion time.
In triggered mode, writing any of the triggered convert modes into the Configuration Register (00h) (that is, MODE bits of the Configuration Register (00h) are set to ‘001’, ‘010’, or ‘011’) triggers a single-shot conversion. This action produces a single set of measurements; thus, to trigger another single-shot conversion, the Configuration Register (00h) must be written to a second time, even if the mode does not change.
In addition to the two operating modes (continuous and triggered), the device also has a power-down mode that reduces the quiescent current and turns off current into the device inputs, reducing the impact of supply drain when the device is not being used. Full recovery from power-down mode requires 40µs. The registers of the device can be written to and read from while the device is in power-down mode. The device remains in power-down mode until one of the active modes settings are written into the Configuration Register (00h) .
Although the device can be read at any time, and the data from the last conversion remain available, the Conversion Ready flag bit (Mask/Enable Register, CVRF bit) is provided to help coordinate one-shot or triggered conversions. The Conversion Ready flag (CVRF) bit is set after all conversions, averaging, and multiplication operations are complete.
The Conversion Ready flag (CVRF) bit clears under these conditions:
The Current and Power are calculated following shunt voltage and bus voltage measurements as shown in Figure 19. Current is calculated following a shunt voltage measurement based on the value set in the Calibration Register. If there is no value loaded into the Calibration Register, the current value stored is zero. Power is calculated following the bus voltage measurement based on the previous current calculation and bus voltage measurement. If there is no value loaded in the Calibration Register, the power value stored is also zero. Again, these calculations are performed in the background and do not add to the overall conversion time. These current and power values are considered intermediate results (unless the averaging is set to 1) and are stored in an internal accumulation register, not the corresponding output registers. Following every measured sample, the newly-calculated values for current and power are appended to this accumulation register until all of the samples have been measured and averaged based on the number of averages set in the Configuration Register (00h).
In addition to the current and power accumulating after every sample, the shunt and bus voltage measurements are also collected. After all of the samples have been measured and the corresponding current and power calculations have been made, the accumulated average for each of these parameters is then loaded to the corresponding output registers, where they can then be read.
The INA226 has a single Alert Limit Register (07h), that allows the Alert pin to be programmed to respond to a single user-defined event or to a Conversion Ready notification if desired. The Mask/Enable Register allows the user to select from one of the five available functions to monitor and/or set the Conversion Ready bit to control the response of the Alert pin. Based on the function being monitored, the user would then enter a value into the Alert Limit Register to set the corresponding threshold value that asserts the Alert pin.
The Alert pin allows for one of several available alert functions to be monitored to determine if a user-defined threshold has been exceeded. The five alert functions that can be monitored are:
The Alert pin is an open-drain output. This pin is asserted when the alert function selected in the Mask/Enable Register exceeds the value programmed into the Alert Limit Register. Only one of these alert functions can be enabled and monitored at a time. If multiple alert functions are enabled, the selected function in the highest significant bit position takes priority and responds to the Alert Limit Register value. For example, if the Shunt Voltage Over-Limit function and the Shunt Voltage Under-Limit function are both selected, the Alert pin asserts when the Shunt Voltage Register exceeds the value in the Alert Limit Register.
The Conversion Ready state of the device can also be monitored at the Alert pin to inform the user when the device has completed the previous conversion and is ready to begin a new conversion. Conversion Ready can be monitored at the Alert pin along with one of the alert functions. If an alert function and the Conversion Ready are both enabled to be monitored at the Alert pin, after the Alert pin is asserted, the Mask/Enable Register must be read following the alert to determine the source of the alert. By reading the Conversion Ready Flag (CVRF, bit 3), and the Alert Function Flag (AFF, bit 4) in the Mask/Enable Register, the source of the alert can be determined. If the Conversion Ready feature is not desired and the CNVR bit is not set, the Alert pin only responds to an exceeded alert limit based on the alert function enabled.
If the alert function is not used, the Alert pin can be left floating without impacting the operation of the device.
Refer to Figure 19 to see the relative timing of when the value in the Alert Limit Register is compared to the corresponding converted value. For example, if the alert function that is enabled is Shunt Voltage Over-Limit (SOL), following every shunt voltage conversion the value in the Alert Limit Register is compared to the measured shunt voltage to determine if the measurements has exceeded the programmed limit. The AFF, bit 4 of the Mask/Enable Register, asserts high any time the measured voltage exceeds the value programmed into the Alert Limit Register. In addition to the AFF being asserted, the Alert pin is asserted based on the Alert Polarity Bit (APOL, bit 1 of the Mask/Enable Register). If the Alert Latch is enabled, the AFF and Alert pin remain asserted until either the Configuration Register (00h) is written to or the Mask/Enable Register is read.
The Bus Voltage alert functions compare the measured bus voltage to the Alert Limit Register following every bus voltage conversion and assert the AFF bit and Alert pin if the limit threshold is exceeded.
The Power Over-Limit alert function is also compared to the calculated power value following every bus voltage measurement conversion and asserts the AFF bit and Alert pin if the limit threshold is exceeded.
The INA226 device offers programmable conversion times (tCT) for both the shunt voltage and bus voltage measurements. The conversion times for these measurements can be selected from as fast as 140 μs to as long as 8.244 ms. The conversion time settings, along with the programmable averaging mode, allow the device to be configured to optimize the available timing requirements in a given application. For example, if a system requires that data be read every 5ms, the device could be configured with the conversion times set to 588 μs for both shunt and bus voltage measurements and the averaging mode set to 4. This configuration results in the data updating approximately every 4.7ms. The device could also be configured with a different conversion time setting for the shunt and bus voltage measurements. This type of approach is common in applications where the bus voltage tends to be relatively stable. This situation can allow for the time focused on the bus voltage measurement to be reduced relative to the shunt voltage measurement. The shunt voltage conversion time could be set to 4.156 ms with the bus voltage conversion time set to 588 μs, with the averaging mode set to 1. This configuration also results in data updating approximately every 4.7 ms.
There are trade-offs associated with the settings for conversion time and the averaging mode used. The averaging feature can significantly improve the measurement accuracy by effectively filtering the signal. This approach allows the device to reduce any noise in the measurement that may be caused by noise coupling into the signal. A greater number of averages enables the device to be more effective in reducing the noise component of the measurement.
The conversion times selected can also have an impact on the measurement accuracy. Figure 20 shows multiple conversion times to illustrate the impact of noise on the measurement. In order to achieve the highest accuracy measurement possible, use a combination of the longest allowable conversion times and highest number of averages, based on the timing requirements of the system.
Measuring current is often noisy, and such noise can be difficult to define. The INA226 device offers several options for filtering by allowing the conversion times and number of averages to be selected independently in the Configuration Register (00h). The conversion times can be set independently for the shunt voltage and bus voltage measurements to allow added flexibility in configuring the monitoring of the power-supply bus.
The internal ADC is based on a delta-sigma (ΔΣ) front-end with a 500 kHz (±30%) typical sampling rate. This architecture has good inherent noise rejection; however, transients that occur at or very close to the sampling rate harmonics can cause problems. Because these signals are at 1 MHz and higher, they can be managed by incorporating filtering at the input of the device. The high frequency enables the use of low-value series resistors on the filter with negligible effects on measurement accuracy. In general, filtering the device input is only necessary if there are transients at exact harmonics of the 500 kHz (±30%) sampling rate (greater than 1 MHz). Filter using the lowest possible series resistance (typically 10 Ω or less) and a ceramic capacitor. Recommended values for this capacitor are between 0.1 μF and 1 μF. Figure 21 shows the device with a filter added at the input.
Overload conditions are another consideration for the device inputs. The device inputs are specified to tolerate 40 V across the inputs. A large differential scenario might be a short to ground on the load side of the shunt. This type of event can result in full power-supply voltage across the shunt (as long the power supply or energy storage capacitors support it). Removing a short to ground can result in inductive kickbacks that could exceed the 40-V differential and common-mode rating of the device. Inductive kickback voltages are best controlled by Zener-type transient-absorbing devices (commonly called transzorbs) combined with sufficient energy storage capacitance. See the TI Design, Transient Robustness for Current Shunt Monitors (TIDU473), which describes a high-side current shunt monitor used to measure the voltage developed across a current-sensing resistor when current passes through it.
In applications that do not have large energy storage electrolytics on one or both sides of the shunt, an input overstress condition may result from an excessive dV/dt of the voltage applied to the input. A hard physical short is the most likely cause of this event, particularly in applications with no large electrolytics present. This problem occurs because an excessive dV/dt can activate the ESD protection in the device in systems where large currents are available. Testing demonstrates that the addition of 10-Ω resistors in series with each input of the device sufficiently protects the inputs against this dV/dt failure up to the 40-V rating of the device. Selecting these resistors in the range noted has minimal effect on accuracy.
An important aspect of the INA226 device is that it does not necessarily measure current or power. The device measures both the differential voltage applied between the IN+ and IN- input pins and the voltage applied to the VBUS pin. In order for the device to report both current and power values, the user must program the resolution of the Current Register (04h) and the value of the shunt resistor present in the application to develop the differential voltage applied between the input pins. The Power Register (03h) is internally set to be 25 times the programmed Current_LSB. Both the Current_LSB and shunt resistor value are used in the calculation of the Calibration Register value the device uses to calculate the corresponding current and power values based on the measured shunt and bus voltages.
The Calibration Register is calculated based on Equation 1. This equation includes the term Current_LSB, which is the programmed value for the LSB for the Current Register (04h). The user uses this value to convert the value in the Current Register (04h) to the actual current in amperes. The highest resolution for the Current Register (04h) can be obtained by using the smallest allowable Current_LSB based on the maximum expected current as shown in Equation 2. While this value yields the highest resolution, it is common to select a value for the Current_LSB to the nearest round number above this value to simplify the conversion of the Current Register (04h) and Power Register (03h) to amperes and watts respectively. The RSHUNT term is the value of the external shunt used to develop the differential voltage across the input pins.
After programming the Calibration Register, the Current Register (04h) and Power Register (03h) update accordingly based on the corresponding shunt voltage and bus voltage measurements. Until the Calibration Register is programmed, the Current Register (04h) and Power Register (03h) remain at zero.
Figure 27 shows a nominal 10-A load that creates a differential voltage of 20 mV across a 2-mΩ shunt resistor. The bus voltage for the INA226 is measured at the external VBUS input pin, which in this example is connected to the IN– pin to measure the voltage level delivered to the load. For this example, the VBUS pin measures less than 12 V because the voltage at the IN– pin is 11.98 V as a result of the voltage drop across the shunt resistor.
For this example, assuming a maximum expected current of 15 A, the Current_LSB is calculated to be 457.7 μA/bit using Equation 2. Using a value for the Current_LSB of 500 μA/Bit or 1 mA/Bit would significantly simplify the conversion from the Current Register (04h) and Power Register (03h) to amperes and watts. For this example, a value of 1 mA/bit was chosen for the Current_LSB. Using this value for the Current_LSB does trade a small amount of resolution for having a simpler conversion process on the user side. Using Equation 1 in this example with a Current_LSB value of 1 mA/bit and a shunt resistor of 2 mΩ results in a Calibration Register value of 2560, or A00h.
The Current Register (04h) is then calculated by multiplying the decimal value of the Shunt Voltage Register (01h) contents by the decimal value of the Calibration Register and then dividing by 2048, as shown in Equation 3. For this example, the Shunt Voltage Register contains a value of 8,000 (representing 20 mV), which is multiplied by the Calibration Register value of 2560 and then divided by 2048 to yield a decimal value for the Current Register (04h) of 10000, or 2710h. Multiplying this value by 1 mA/bit results in the original 10-A level stated in the example.
The LSB for the Bus Voltage Register (02h) is a fixed 1.25 mV/bit, which means that the 11.98 V present at the VBUS pin results in a register value of 2570h, or a decimal equivalent of 9584. Note that the MSB of the Bus Voltage Register (02h) is always zero because the VBUS pin is only able to measure positive voltages.
The Power Register (03h) is then be calculated by multiplying the decimal value of the Current Register, 10000, by the decimal value of the Bus Voltage Register (02h), 9584, and then dividing by 20,000, as defined in Equation 4. For this example, the result for the Power Register (03h) is 12B8h, or a decimal equivalent of 4792. Multiplying this result by the power LSB (25 times the [1 × 10–3 Current_LSB]) results in a power calculation of (4792 × 25 mW/bit), or 119.82 W. The power LSB has a fixed ratio to the Current_LSB of 25. For this example, a programmed 1 mA/bit Current_LSB results in a power LSB of 25 mW/bit. This ratio is internally programmed to ensure that the scaling of the power calculation is within an acceptable range. A manual calculation for the power being delivered to the load would use a bus voltage of 11.98 V (12 VCM – 20 mV shunt drop) multiplied by the load current of 10 A to give a result of 119.8 W.
Table 1 lists the steps for configuring, measuring, and calculating the values for current and power for this device.
|Step 1||Configuration Register||00h||4127h||—||—||—|
|Step 2||Shunt Register||01h||1F40h||8000||2.5 µV||20 mV|
|Step 3||Bus Voltage Register||02h||2570h||9584||1.25 mV||11.98 V|
|Step 4||Calibration Register||05h||A00h||2560||—||—|
|Step 5||Current Register||04h||2710||10000||1 mA||10 A|
|Step 6||Power Register||03h||12B8h||4792||25 mW||119.82 W|
The Calibration Register enables the user to scale the Current Register (04h) and Power Register (03h) to the most useful value for a given application. For example, set the Calibration Register such that the largest possible number is generated in the Current Register (04h) or Power Register (03h) at the expected full-scale point. This approach yields the highest resolution using the previously calculated minimum Current_LSB in the equation for the Calibration Register. The Calibration Register can also be selected to provide values in the Current Register (04h) and Power Register (03h) that either provide direct decimal equivalents of the values being measured, or yield a round LSB value for each corresponding register. After these choices have been made, the Calibration Register also offers possibilities for end user system-level calibration. After determining the exact current by using an external ammeter, the value of the Calibration Register can then be adjusted based on the measured current result of the INA226 to cancel the total system error as shown in Equation 5.
The device can be used without any programming if it is only necessary to read a shunt voltage drop and bus voltage with the default power-on reset configuration and continuous conversion of shunt and bus voltages.
Without programming the device Calibration Register, the device is unable to provide either a valid current or power value, because these outputs are both derived using the values loaded into the Calibration Register.
The default power-up states of the registers are shown in the Register Maps section of this data sheet. These registers are volatile, and if programmed to a value other than the default values shown in Table 4, they must be re-programmed at every device power-up. Detailed information on programming the Calibration Register specifically is given in the Programming section and calculated based on Equation 1.
The INA226 offers compatibility with both I2C and SMBus interfaces. The I2C and SMBus protocols are essentially compatible with one another.
The I2C interface is used throughout this data sheet as the primary example, with SMBus protocol specified only when a difference between the two systems is discussed. Two lines, SCL and SDA, connect the device to the bus. Both SCL and SDA are open-drain connections.
The device that initiates a data transfer is called a master, and the devices controlled by the master are slaves. The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates START and STOP conditions.
To address a specific device, the master initiates a start condition by pulling the data signal line (SDA) from a high to a low logic level while SCL is high. All slaves on the bus shift in the slave address byte on the rising edge of SCL, with the last bit indicating whether a read or write operation is intended. During the ninth clock pulse, the slave being addressed responds to the master by generating an Acknowledge and pulling SDA low.
Data transfer is then initiated and eight bits of data are sent, followed by an Acknowledge bit. During data transfer, SDA must remain stable while SCL is high. Any change in SDA while SCL is high is interpreted as a start or stop condition.
After all data have been transferred, the master generates a stop condition, indicated by pulling SDA from low to high while SCL is high. The device includes a 28 ms timeout on its interface to prevent locking up the bus.
To communicate with the INA226, the master must first address slave devices via a slave address byte. The slave address byte consists of seven address bits and a direction bit that indicates whether the action is to be a read or write operation.
The device has two address pins, A0 and A1. Table 2 lists the pin logic levels for each of the 16 possible addresses. The device samples the state of pins A0 and A1 on every bus communication. Establish the pin states before any activity on the interface occurs.
The INA226 operates only as a slave device on both the I2C bus and the SMBus. Connections to the bus are made via the open-drain SDA and SCL lines. The SDA and SCL pins feature integrated spike suppression filters and Schmitt triggers to minimize the effects of input spikes and bus noise. Although the device integrates spike suppression into the digital I/O lines, proper layout techniques help minimize the amount of coupling into the communication lines. This noise introduction could occur from capacitively coupling signal edges between the two communication lines themselves or from other switching noise sources present in the system. Routing traces in parallel with ground in between layers on a printed circuit board (PCB) typically reduces the effects of coupling between the communication lines. Shielded communication lines reduces the possibility of unintended noise coupling into the digital I/O lines that could be incorrectly interpreted as start or stop commands.
The INA226 supports the transmission protocol for fast mode (1 kHz to 400 kHz) and high-speed mode (1 kHz to 2.94 MHz). All data bytes are transmitted most significant byte first.
Accessing a specific register on the INA226 is accomplished by writing the appropriate value to the register pointer. Refer to Table 4 for a complete list of registers and corresponding addresses. The value for the register pointer (as shown in Figure 25) is the first byte transferred after the slave address byte with the R/W bit low. Every write operation to the device requires a value for the register pointer.
Writing to a register begins with the first byte transmitted by the master. This byte is the slave address, with the R/W bit low. The device then acknowledges receipt of a valid address. The next byte transmitted by the master is the address of the register which data is written to. This register address value updates the register pointer to the desired register. The next two bytes are written to the register addressed by the register pointer. The device acknowledges receipt of each data byte. The master may terminate data transfer by generating a start or stop condition.
When reading from the device , the last value stored in the register pointer by a write operation determines which register is read during a read operation. To change the register pointer for a read operation, a new value must be written to the register pointer. This write is accomplished by issuing a slave address byte with the R/W bit low, followed by the register pointer byte. No additional data are required. The master then generates a start condition and sends the slave address byte with the R/W bit high to initiate the read command. The next byte is transmitted by the slave and is the most significant byte of the register indicated by the register pointer. This byte is followed by an Acknowledge from the master; then the slave transmits the least significant byte. The master acknowledges receipt of the data byte. The master may terminate data transfer by generating a Not-Acknowledge after receiving any data byte, or generating a start or stop condition. If repeated reads from the same register are desired, it is not necessary to continually send the register pointer bytes; the device retains the register pointer value until it is changed by the next write operation.
Register bytes are sent most-significant byte first, followed by the least significant byte.
When the bus is idle, both the SDA and SCL lines are pulled high by the pullup resistors. The master generates a start condition followed by a valid serial byte containing high-speed (HS) master code 00001XXX. This transmission is made in fast (400 kHz) or standard (100 kHz) (F/S) mode at no more than 400 kHz. The device does not acknowledge the HS master code, but does recognize it and switches its internal filters to support 2.94 MHz operation.
The master then generates a repeated start condition (a repeated start condition has the same timing as the start condition). After this repeated start condition, the protocol is the same as F/S mode, except that transmission speeds up to 2.94 MHz are allowed. Instead of using a stop condition, use repeated start conditions to secure the bus in HS-mode. A stop condition ends the HS-mode and switches all the internal filters of the device to support the F/S mode.
|PARAMETER||FAST MODE||HIGH-SPEED MODE||UNIT|
|SCL operating frequency||f(SCL)||0.001||0.4||0.001||2.94||MHz|
|Bus free time between stop and start conditions||t(BUF)||600||160||ns|
|Hold time after repeated START condition.
After this period, the first clock is generated.
|Repeated start condition setup time||t(SUSTA)||100||100||ns|
|STOP condition setup time||t(SUSTO)||100||100||ns|
|Data hold time||t(HDDAT)||10||900||10||100||ns|
|Data setup time||t(SUDAT)||100||20||ns|
|SCL clock low period||t(LOW)||1300||200||ns|
|SCL clock high period||t(HIGH)||600||60||ns|
|Data fall time||tF||300||80||ns|
|Clock fall time||tF||300||40||ns|
|Clock rise time||tR||300||40||ns|
|Clock/data rise time for SCLK ≤ 100kHz||tR||1000||ns|
The INA226 is designed to respond to the SMBus Alert Response address. The SMBus Alert Response provides a quick fault identification for simple slave devices. When an Alert occurs, the master can broadcast the Alert Response slave address (0001 100) with the Read/Write bit set high. Following this Alert Response, any slave device that generates an alert identifies itself by acknowledging the Alert Response and sending its address on the bus.
The Alert Response can activate several different slave devices simultaneously, similar to the I2C General Call. If more than one slave attempts to respond, bus arbitration rules apply. The losing device does not generate an Acknowledge and continues to hold the Alert line low until the interrupt is cleared.
The INA226 uses a bank of registers for holding configuration settings, measurement results, minimum/maximum limits, and status information. Table 4 summarizes the device registers; refer to the Functional Block Diagram section for an illustration of the registers.
All 16-bit device registers are two 8-bit bytes via the I2C interface.
|POINTER ADDRESS||REGISTER NAME||FUNCTION||POWER-ON RESET||TYPE(1)|
|00h||Configuration Register||All-register reset, shunt voltage and bus voltage ADC conversion times and averaging, operating mode.||01000001 00100111||4127||R/W|
|01h||Shunt Voltage Register||Shunt voltage measurement data.||00000000 00000000||0000||R|
|02h||Bus Voltage Register||Bus voltage measurement data.||00000000 00000000||0000||R|
|03h||Power Register(2)||Contains the value of the calculated power being delivered to the load.||00000000 00000000||0000||R|
|04h||Current Register(2)||Contains the value of the calculated current flowing through the shunt resistor.||00000000 00000000||0000||R|
|05h||Calibration Register||Sets full-scale range and LSB of current and power measurements. Overall system calibration.||00000000 00000000||0000||R/W|
|06h||Mask/Enable Register||Alert configuration and Conversion Ready flag.||00000000 00000000||0000||R/W|
|07h||Alert Limit Register||Contains the limit value to compare to the selected Alert function.||00000000 00000000||0000||R/W|
|FEh||Manufacturer ID Register||Contains unique manufacturer identification number.||0101010001001001||5449||R|
|FFh||Die ID Register||Contains unique die identification number.||0010001001100000||2260||R|
The Configuration Register settings control the operating modes for the device. This register controls the conversion time settings for both the shunt and bus voltage measurements as well as the averaging mode used. The operating mode that controls what signals are selected to be measured is also programmed in the Configuration Register .
The Configuration Register can be read from at any time without impacting or affecting the device settings or a conversion in progress. Writing to the Configuration Register halts any conversion in progress until the write sequence is completed resulting in a new conversion starting based on the new contents of the Configuration Register (00h). This halt prevents any uncertainty in the conditions used for the next completed conversion.
|Bit 15||Setting this bit to '1' generates a system reset that is the same as power-on reset. Resets all registers to default values; this bit self-clears.|
|Bits 9–11||Determines the number of samples that are collected and averaged. Table 6 shows all the AVG bit settings and related number of averages for each bit setting.|
|VBUSCT:||Bus Voltage Conversion Time|
|Bits 6–8||Sets the conversion time for the bus voltage measurement. Table 7 shows the VBUSCT bit options and related conversion times for each bit setting.|
|VSHCT:||Shunt Voltage Conversion Time|
|Bits 3–5||Sets the conversion time for the shunt voltage measurement. Table 8 shows the VSHCT bit options and related conversion times for each bit setting.|
|Bits 0-2||Selects continuous, triggered, or power-down mode of operation. These bits default to continuous shunt and bus measurement mode. The mode settings are shown in Table 9.|
|0||0||0||Power-Down (or Shutdown)|
|0||0||1||Shunt Voltage, Triggered|
|0||1||0||Bus Voltage, Triggered|
|0||1||1||Shunt and Bus, Triggered|
|1||0||0||Power-Down (or Shutdown)|
|1||0||1||Shunt Voltage, Continuous|
|1||1||0||Bus Voltage, Continuous|
|1||1||1||Shunt and Bus, Continuous|
The Shunt Voltage Register stores the current shunt voltage reading, VSHUNT. Negative numbers are represented in two's complement format. Generate the two's complement of a negative number by complementing the absolute value binary number and adding 1. An MSB = '1' denotes a negative number.
Example: For a value of VSHUNT = –80 mV:
If averaging is enabled, this register displays the averaged value.
Full-scale range = 81.92 mV (decimal = 7FFF); LSB: 2.5 μV.
The Bus Voltage Register stores the most recent bus voltage reading, VBUS.
If averaging is enabled, this register displays the averaged value.
Full-scale range = 40.96 V (decimal = 7FFF); LSB = 1.25 mV.
If averaging is enabled, this register displays the averaged value.
The Power Register LSB is internally programmed to equal 25 times the programmed value of the Current_LSB.
The Power Register records power in Watts by multiplying the decimal values of the Current Register with the decimal value of the Bus Voltage Register according to Equation 4.
If averaging is enabled, this register displays the averaged value.
The value of the Current Register is calculated by multiplying the decimal value in the Shunt Voltage Register with the decimal value of the Calibration Register, according to Equation 3.
This register provides the device with the value of the shunt resistor that was present to create the measured differential voltage. It also sets the resolution of the Current Register. Programming this register sets the Current_LSB and the Power_LSB. This register is also suitable for use in overall system calibration. See the Programming the Calibration Register for additional information on programming the Calibration Register.
The Mask/Enable Register selects the function that is enabled to control the Alert pin as well as how that pin functions. If multiple functions are enabled, the highest significant bit position Alert Function (D15-D11) takes priority and responds to the Alert Limit Register.
|SOL:||Shunt Voltage Over-Voltage|
|Bit 15||Setting this bit high configures the Alert pin to be asserted if the shunt voltage measurement following a conversion exceeds the value programmed in the Alert Limit Register.|
|SUL:||Shunt Voltage Under-Voltage|
|Bit 14||Setting this bit high configures the Alert pin to be asserted if the shunt voltage measurement following a conversion drops below the value programmed in the Alert Limit Register.|
|BOL:||Bus Voltage Over-Voltage|
|Bit 13||Setting this bit high configures the Alert pin to be asserted if the bus voltage measurement following a conversion exceeds the value programmed in the Alert Limit Register.|
|BUL:||Bus Voltage Under-Voltage|
|Bit 12||Setting this bit high configures the Alert pin to be asserted if the bus voltage measurement following a conversion drops below the value programmed in the Alert Limit Register.|
|Bit 11||Setting this bit high configures the Alert pin to be asserted if the Power calculation made following a bus voltage measurement exceeds the value programmed in the Alert Limit Register.|
|Bit 10||Setting this bit high configures the Alert pin to be asserted when the Conversion Ready Flag, Bit 3, is asserted indicating that the device is ready for the next conversion.|
|AFF:||Alert Function Flag|
|Bit 4||While only one Alert Function can be monitored at the Alert pin at a time, the Conversion Ready can also be enabled to assert the Alert pin. Reading the Alert Function Flag following an alert allows the user to determine if the Alert Function was the source of the Alert.
When the Alert Latch Enable bit is set to Latch mode, the Alert Function Flag bit clears only when the Mask/Enable Register is read. When the Alert Latch Enable bit is set to Transparent mode, the Alert Function Flag bit is cleared following the next conversion that does not result in an Alert condition.
|CVRF:||Conversion Ready Flag|
|Bit 3||Although the device can be read at any time, and the data from the last conversion is available, the Conversion Ready Flag bit is provided to help coordinate one-shot or triggered conversions. The Conversion Ready Flag bit is set after all conversions, averaging, and multiplications are complete. Conversion Ready Flag bit clears under the following conditions:
1.) Writing to the Configuration Register (except for Power-Down selection)
2.) Reading the Mask/Enable Register
|OVF:||Math Overflow Flag|
|Bit 2||This bit is set to '1' if an arithmetic operation resulted in an overflow error. It indicates that current and power data may be invalid.|
|APOL:||Alert Polarity bit; sets the Alert pin polarity.|
|Bit 1||1 = Inverted (active-high open collector)
0 = Normal (active-low open collector) (default)
|LEN:||Alert Latch Enable; configures the latching feature of the Alert pin and Alert Flag bits.|
|Bit 0||1 = Latch enabled
0 = Transparent (default)
When the Alert Latch Enable bit is set to Transparent mode, the Alert pin and Flag bit resets to the idle states when the fault has been cleared. When the Alert Latch Enable bit is set to Latch mode, the Alert pin and Alert Flag bit remains active following a fault until the Mask/Enable Register has been read.
The Alert Limit Register contains the value used to compare to the register selected in the Mask/Enable Register to determine if a limit has been exceeded.
The Manufacturer ID Register stores a unique identification number for the manufacturer.
|ID:||Manufacturer ID Bits|
|Bits 0-15||Stores the manufacturer identification bits|
The Die ID Register stores a unique identification number and the revision ID for the die.
|DID:||Device ID Bits|
|Bits 4-15||Stores the device identification bits|
|RID:||Die Revision ID Bits|
|Bit 0-3||Stores the device revision identification bits|