JAJSGE1A October 2018 – October 2019 ISO1042-Q1
A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 33). Layer stacking should be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency signal layer.
Suggested placement and routing of ISO1042-Q1 bypass capacitors and optional TVS diodes is shown in Figure 34 and Figure 35. In particular, place the VCC2 bypass capacitors on the top layer, as close to the device pins as possible, and complete the connection to the VCC2 and GND2 pins without using vias. Note that the SOIC-16 variant needs two VCC2 bypass capacitor, one on each VCC2 pin.
If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the power and ground plane of each power system can be placed closer together, thus increasing the high-frequency bypass capacitance significantly.
For detailed layout recommendations, refer to the Digital Isolator Design Guide.