JAJSDX8E June   2017  – August 2018 ISO1211 , ISO1212

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      アプリケーション図
      2.      従来のソリューションと比較した、ISO121xデバイスによる基板の温度の低下
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
    2.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Ratings
    6. 7.6  Insulation Specifications
    7. 7.7  Safety-Related Certifications
    8. 7.8  Safety Limiting Values
    9. 7.9  Electrical Characteristics—DC Specification
    10. 7.10 Switching Characteristics—AC Specification
    11. 7.11 Insulation Characteristics Curves
    12. 7.12 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Test Circuits
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Sinking Inputs
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Setting Current Limit and Voltage Thresholds
          2. 10.2.1.2.2 Thermal Considerations
          3. 10.2.1.2.3 Designing for 48-V Systems
          4. 10.2.1.2.4 Designing for Input Voltages Greater Than 60 V
          5. 10.2.1.2.5 Surge, ESD, and EFT Tests
          6. 10.2.1.2.6 Multiplexing the Interface to the Host Controller
          7. 10.2.1.2.7 Status LEDs
        3. 10.2.1.3 Application Curve
      2. 10.2.2 Sourcing Inputs
      3. 10.2.3 Sourcing and Sinking Inputs (Bidirectional Inputs)
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイス・サポート
      1. 13.1.1 開発サポート
    2. 13.2 ドキュメントのサポート
      1. 13.2.1 関連資料
    3. 13.3 関連リンク
    4. 13.4 ドキュメントの更新通知を受け取る方法
    5. 13.5 コミュニティ・リソース
    6. 13.6 商標
    7. 13.7 静電気放電に関する注意事項
    8. 13.8 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • D|8
サーマルパッド・メカニカル・データ
発注情報

12.1 Layout Guidelines

The board layout for ISO1211 and ISO1212 can be completed in two layers. On the field side, place RSENSE, CIN, and RTHR on the top layer. Use the bottom layer as the field ground (FGND) plane. TI recommends using RSENSE and CIN in 0603 footprint for a compact layout, although larger sizes (0805) can also be used. The CIN capacitor is a 50-V capacitor and is available in the 0603 footprint. Keep CIN as close to the ISO121x device as possible. The SUB pin on the ISO1211 device and the SUB1 and SUB2 pins on the ISO1212 device should be left unconnected. For group isolated design, use vias to connect the FGND pins of the ISO121x device to the bottom FGND plane. The placement of the RTHR resistor is flexible, although the resistor pin connected to external high voltage should not be placed within 4 mm of the ISO121x device pins or the CIN and RSENSE pins to avoid flashover during EMC tests.

Only a decoupling capacitor is required on side 1. Place this capacitor on the top-layer, with the bottom layer for GND1.

If a board with more than two layers is used, placing two ISO121x devices on the top-and bottom layers (back-to-back) is possible to achieve a more compact board. The inner layers can be used for FGND.

Figure 31 and Figure 32 show the example layouts.

In some designs, placing the LED on the field side is desirable although it is powered from VCC1. In such cases, the signal carrying current to the LED can be routed in an inner layer without compromising the isolation of the digital-input module as shown in Figure 33. The LED must be placed with at least 4-mm spacing between other components and connections on side 1 to ensure adequate isolation.