JAJSGA9C September   2018  – September 2019 ISO1500

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     概略回路図
  4. 4 改訂履歴
  5. 5 概要 (続き)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Ratings
    6. 7.6  Insulation Specifications
    7. 7.7  Safety-Related Certifications
    8. 7.8  Safety Limiting Values
    9. 7.9  Electrical Characteristics: Driver
    10. 7.10 Electrical Characteristics: Receiver
    11. 7.11 Supply Current Characteristics: Side 1(ICC1)
    12. 7.12 Supply Current Characteristics: Side 2(ICC2)
    13. 7.13 Switching Characteristics: Driver
    14. 7.14 Switching Characteristics: Receiver
    15. 7.15 Insulation Characteristics Curves
    16. 7.16 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Electromagnetic Compatibility (EMC) Considerations
      2. 9.3.2 Failsafe Receiver
      3. 9.3.3 Thermal Shutdown
      4. 9.3.4 Glitch-Free Power Up and Power Down
    4. 9.4 Device Functional Modes
      1. 9.4.1 Device I/O Schematics
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Data Rate and Bus Length
        2. 10.2.2.2 Stub Length
        3. 10.2.2.3 Bus Loading
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 PCB Material
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントのサポート
      1. 13.1.1 関連資料
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 コミュニティ・リソース
    4. 13.4 商標
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.4 Device Functional Modes

Table 2 shows the driver functional modes.

Table 2. Driver Functional Table(1)

VCC1 VCC2 INPUT D DRIVER ENABLE DE OUTPUTS
A B
PU PU H H H L
L H L H
X L Hi-Z Hi-Z
X Open Hi-Z Hi-Z
Open H H L
PD(2) PU X X Hi-Z Hi-Z
X PD X X Hi-Z Hi-Z
(1) PU = Powered Up; PD = Powered Down; H = High Level; L = Low level; X = Irrelevant, Hi-Z = High impedance state
(2) A strongly driven input signal can weakly power the floating VCC1 through an internal protection diode and cause an undetermined output.

When the driver enable pin, DE, is logic high, the differential outputs, A and B, follow the logic states at data input, D. A logic high at the D input causes the A output to go high and the B output to go low. Therefore the differential output voltage defined by Equation 1 is positive.

Equation 1. VOD = VA – VB

A logic low at the D input causes the B output to go high and the A output to go low. Therefore the differential output voltage defined by Equation 1 is negative. A logic low at the DE input causes both outputs to go to the high-impedance (Hi-Z) state. The logic state at the D pin is irrelevant when the DE input is logic low. The DE pin has an internal pulldown resistor to ground. The driver is disabled (bus outputs are in the Hi-Z) by default when the DE pin is left open. The D pin has an internal pullup resistor. The A output goes high and the B output goes low when the D pin is left open while the driver enabled.

Table 3 shows the receiver functional modes.

Table 3. Receiver Functional Table(1)

VCC1 VCC2 DIFFERENTIAL INPUT RECEIVER ENABLE RE OUTPUT R
VID = VA – VB
PU PU –0.02 V ≤ VID L H
–0.2 V < VID < 0.02 V L Indeterminate
VID≤ –0.2 V L L
X H Hi-Z
X Open Hi-Z
Open, Short, Idle L H
PD(2) PU X X Hi-Z
PU PD X L H
PD(2) PD X X Hi-Z
(1) PU = Powered Up; PD = Powered Down; H = Logic High; L= Logic Low; X = Irrelevant, Hi-Z = High Impedance (OFF) state
(2) A strongly driven input signal can weakly power the floating VCC1 through an internal protection diode and cause an undetermined output.

The receiver is enabled when the receiver enable pin, RE, is logic low. The receiver output, R, goes high when the differential input voltage defined by Equation 2 is greater than the positive input threshold, VTH+.

Equation 2. VID = VA – VB

The receiver output, R, goes low when the differential input voltage defined by Equation 2 is less than the negative input threshold, VTH–. If the VID voltage is between the VTH+ and VTH– thresholds, the output is indeterminate. The receiver output is in the Hi-Z state and the magnitude and polarity of VID are irrelevant when the RE pin is logic high or left open. The internal biasing of the receiver inputs causes the output to go to a failsafe-high when the transceiver is disconnected from the bus (open-circuit), the bus lines are shorted to one another (short-circuit), or the bus is not actively driven (idle bus).