JAJSGA9C September 2018 – September 2019 ISO1500
A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 34). Layer stacking should be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency signal layer.
Figure 35 shows the recommended placement and routing of the device bypass capacitors and optional TVS diodes. Put the two VCC2 bypass capacitors on the top layer and as near to the device pins as possible. Do not use vias to complete the connection to the VCC2 and GND2 pins. If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the power and ground plane of each power system can be placed closer together, thus increasing the high-frequency bypass capacitance significantly.
Refer to the Digital Isolator Design Guide for detailed layout recommendations.