JAJS331P July   2006  – August 2018 ISO7220A , ISO7220B , ISO7220C , ISO7220M , ISO7221A , ISO7221B , ISO7221C , ISO7221M

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     概略回路図
  4. 4 改訂履歴
  5. 5 说明（续）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Ratings
    6. 7.6  Insulation Specifications
    7. 7.7  Safety-Related Certifications
    8. 7.8  Safety Limiting Values
    9. 7.9  Electrical Characteristics—5-V VCC1 and V CC2 Supplies
    10. 7.10 Electrical Characteristics—5-V VCC1 and 3.3-V VCC2 Supply
    11. 7.11 Electrical Characteristics—3.3-V VCC1 and 5-V VCC2 Supply
    12. 7.12 Electrical Characteristics—3.3-V VCC1 and VCC2 Supplies
    13. 7.13 Electrical Characteristics—2.8-V VCC1 and VCC2 Supplies
    14. 7.14 Switching Characteristics—5-V VCC1 and VCC2 Supplies
    15. 7.15 Switching Characteristics—5-V VCC1 and 3.3-V VCC2 Supply
    16. 7.16 Switching Characteristics—3.3-V CC1 and 5-V VCC2 Supplies
    17. 7.17 Switching Characteristics—3.3-V VCC1 and VCC2 Supplies
    18. 7.18 Switching Characteristics—2.8-V VCC1 and VCC2 Supplies
    19. 7.19 Insulation Characteristics Curves
    20. 7.20 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 PCB Material
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイス・サポート
      1. 13.1.1 開発サポート
    2. 13.2 ドキュメントのサポート
      1. 13.2.1 関連資料
    3. 13.3 関連リンク
    4. 13.4 ドキュメントの更新通知を受け取る方法
    5. 13.5 コミュニティ・リソース
    6. 13.6 商標
    7. 13.7 静電気放電に関する注意事項
    8. 13.8 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.16 Switching Characteristics—3.3-V CC1 and 5-V VCC2 Supplies

VCC1 at 3.3 V ± 10%, VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted.)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH, tPHL Propagation delay ISO722xA, see Figure 14 285 395 605 ns
PWD Pulse-width distortion |tPHL – tPLH|(1) 1 22 ns
tPLH, tPHL Propagation delay ISO722xB, see Figure 14 45 58 75 ns
PWD Pulse-width distortion |tPHL – tPLH|(1) 1 4 ns
tPLH, tPHL Propagation delay ISO722xC, see Figure 14 25 36 48 ns
PWD Pulse-width distortion |tPHL – tPLH|(1) 1 3 ns
tPLH, tPHL Propagation delay ISO722xM, see Figure 14 7 12 21 ns
PWD Pulse-width distortion |tPHL – tPLH|(1) 0.5 1 ns
tsk(pp) Part-to-part skew (2) ISO722xA 190 ns
ISO722xB 17
ISO722xC 10
ISO722xM 5
tsk(o) Channel-to-channel output skew (3) ISO7220A 3 15 ns
ISO7220B 0.6 3
ISO7220C, ISO7220M 0.2 1
tr Output signal rise time See Figure 14 1 ns
tf Output signal fall time 1 ns
tfs Failsafe output delay time from input power loss See Figure 15 3 μs
tjit(pp) Peak-to-peak eye-pattern jitter ISO722xM, 150 Mbps PRBS NRZ data, 5-bit max same polarity input, both channels, see Figure 17, Figure 13 1 ns
ISO722xM, 150 Mbps unrestricted bit run length data input, both channels, see Figure 17 2
(1) Also referred to as pulse skew.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified pins of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
(3) tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical specified loads.