SLLSEP0A July 2015 – March 2016 ISO7820
ISO7820 employs an ON-OFF Keying (OOK) modulation scheme to transmit the digital data across a silicon dioxide based isolation barrier. The transmitter sends a high frequency carrier across the barrier to represent one digital state and sends no signal to represent the other digital state. The receiver demodulates the signal after advanced signal conditioning and produces the output through a buffer stage. These devices also incorporates advanced circuit techniques to maximize the CMTI performance and minimize the radiated emissions due the high frequency carrier and IO buffer switching. The conceptual block diagram of a digital capacitive isolator, Figure 11, shows a functional block diagram of a typical channel.
Also a conceptual detail of how the ON/OFF Keying scheme works is shown in Figure 12.
ISO7820 is available in two channel configurations and default output state options to enable a variety of application uses.
|PRODUCT||CHANNEL DIRECTION||RATED ISOLATION||MAX DATA RATE||DEFAULT OUTPUT|
|ISO7820||2 Forward, 0 Reverse
||5700 VRMS / 8000 VPK (1)||100 Mbps||High|
|ISO7820F||2 Forward, 0 Reverse
||5700 VRMS / 8000 VPK (1)||100 Mbps||Low|
|CLR||External clearance||Shortest terminal-to-terminal distance through air||DW-16||8||mm|
|CPG||External creepage||Shortest terminal-to-terminal distance across the package surface||DW-16||8||mm|
|CTI||Comparative tracking index||DIN EN 60112 (VDE 0303-11); IEC 60112; UL 746A||600||V|
|RIO||Isolation resistance, input to output(1)||VIO = 500 V, TA = 25°C||1012||Ω|
|VIO = 500 V, 100°C ≤ TA ≤ max||1011||Ω|
|CIO||Barrier capacitance, input to output(1)||VIO = 0.4 x sin (2πft), f = 1 MHz||1||pF|
|CI||Input capacitance(2)||VI = VCC/2 + 0.4 x sin (2πft), f = 1 MHz, VCC = 5 V||2||pF|
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance.
Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.
|DTI||Distance through the insulation||Minimum internal gap (internal clearance)||21||21||μm|
|VIOWM||Maximum working isolation voltage||Time dependent dielectric breakdown (TDDB) test||1500||2000||VRMS|
|DIN V VDE V 0884-10 (VDE V 0884-10):2006-12|
|VIOTM||Maximum transient isolation voltage||VTEST = VIOTM
t = 60 sec (qualification)
t= 1 sec (100% production)
|VIOSM||Maximum surge isolation voltage||Test method per IEC 60065, 1.2/50 µs waveform,
VTEST = 1.6 x VIOSM = 12800 VPK(1) (qualification)
|VIORM||Maximum repetitive peak isolation voltage||2121||2828||VPK|
|VPR||Input-to-output test voltage||Method a, After Input/Output safety test subgroup 2/3,
VPR = VIORM x 1.2, t = 10 s,
Partial discharge < 5 pC
|Method a, After environmental tests subgroup 1,
VPR = VIORM x 1.6, t = 10 s,
Partial Discharge < 5 pC
|Method b1,After environmental tests subgroup 1,
VPR = VIORM x 1.875, t = 1 s (100% Production test)
Partial discharge < 5 pC
|RS||Isolation resistance||VIO = 500 V at TS||>109||>109||Ω|
|VISO||Withstanding isolation voltage||VTEST = VISO = 5700 VRMS, t = 60 sec (qualification);
VTEST = 1.2 x VISO = 6840 VRMS , t = 1 sec (100% production)
|Overvoltage category / Installation classification||DW package||Rated mains voltage ≤ 600 VRMS||I–IV|
|Rated mains voltage ≤ 1000 VRMS||I–III|
|DWW package||Rated mains voltage ≤ 1000 VRMS||I–IV|
DW package certifications are complete; DWW package certifications completed for UL and TUV and planned for VDE, CSA, and CQC.
|Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 and DIN EN 60950-1 (VDE 0805 Teil 1):2011-01||Approved under CSA Component Acceptance Notice 5A, IEC 60950-1 and IEC 60601-1||Recognized under UL 1577 Component Recognition Program||Certified according to GB 4943.1-2011||Certified according to
EN 61010-1:2010 (3rd Ed) and
Maximum transient isolation voltage, 8000 VPK;
Maximum repetitive peak isolation voltage, 2121 VPK (DW), 2828 VPK (DWW);
Maximum surge isolation voltage, 8000 VPK
|Reinforced insulation per CSA 60950-1-07+A1+A2 and IEC 60950-1 2nd Ed.,
800 VRMS (DW package) and 1450 VRMS (DWW package) max working voltage (pollution degree 2, material group I);
|Single protection, 5700 VRMS||Reinforced Insulation, Altitude ≤ 5000 m, Tropical Climate, 250 VRMS maximum working voltage||5700 VRMS Reinforced insulation per EN 61010-1:2010 (3rd Ed) up to working voltage of 600 VRMS (DW package) and 1000 VRMS (DWW package)|
|2 MOPP (Means of Patient Protection) per CSA 60601-1:14 and IEC 60601-1 Ed. 3.1,
250 VRMS (354 VPK) max working voltage (DW package)
|5700 VRMS Reinforced insulation per EN 60950-1:2006/A11:2009/
A1:2010/A12:2011/A2:2013 up to working voltage of 800 VRMS (DW package) and 1450 VRMS (DWW package)
|Certificate number: 40040142||Master contract number: 220991||File number: E181974||Certificate number: CQC15001121716||Client ID number: 77311|
|IS||Safety input, output, or supply current for DW-16 package and DWW-16 Packages||RθJA = 84.7°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C||268||mA|
|RθJA = 84.7°C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C||410|
|RθJA = 84.7°C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C||537|
|PS||Safety input, output, or total power||RθJA = 84.7°C/W, TJ = 150°C, TA = 25°C||1476||mW|
|TS||Maximum safety temperature||150||°C|
The maximum safety temperature is the maximum junction temperature specified for the device. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the is that of a device installed on a High-K test board for Leaded Surface Mount Packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance.
ISO7820 functional modes are shown in Table 6.
(DWW Package Only)
|PU||PU||H||H or open||H||Normal Operation:
A channel output assumes the logic state of its input.
|L||H or open||L|
|Open||H or open||Default||Default mode: When INx is open, the corresponding channel output goes to its default high logic state. Default= High for ISO7820 and Low for ISO7820F.|
|X||PU||X||L||Z||A low value of Output Enable causes the outputs to be high- impedance.|
|PD||PU||X||H or open||Default||Default mode: When VCCI is unpowered, a channel output assumes the logic state based on the selected default option.Default= High for ISO7820 and Low for ISO7820F.
When VCCI transitions from unpowered to powered-up, a channel output assumes the logic state of its input.
When VCCI transitions from powered-up to unpowered, channel output assumes the selected default state.
|X||PD||X||X||Undetermined||When VCCO is unpowered, a channel output is undetermined (2).
When VCCO transitions from unpowered to powered-up, a channel output assumes the logic state of its input