JAJSGG1E October   2018  – June 2021 IWR6443 , IWR6843

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 説明
  4. 4 機能ブロック図
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagram
    2. 7.2 Signal Descriptions
      1. 7.2.1 Signal Descriptions - Digital
      2. 7.2.2 Signal Descriptions - Analog
    3. 7.3 Pin Attributes
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Power-On Hours (POH)
    4. 8.4  Recommended Operating Conditions
    5. 8.5  Power Supply Specifications
    6. 8.6  Power Consumption Summary
    7. 8.7  RF Specification
    8. 8.8  CPU Specifications
    9. 8.9  Thermal Resistance Characteristics for FCBGA Package [ABL0161]
    10. 8.10 Timing and Switching Characteristics
      1. 8.10.1  Power Supply Sequencing and Reset Timing
      2. 8.10.2  Input Clocks and Oscillators
        1. 8.10.2.1 Clock Specifications
      3. 8.10.3  Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 8.10.3.1 Peripheral Description
        2. 8.10.3.2 MibSPI Transmit and Receive RAM Organization
          1. 8.10.3.2.1 SPI Timing Conditions
          2. 8.10.3.2.2 SPI Master Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input) (1) (1) (1)
          3. 8.10.3.2.3 SPI Master Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input) (1) (1) (1)
        3. 8.10.3.3 SPI Slave Mode I/O Timings
          1. 8.10.3.3.1 SPI Slave Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output) (1) (1) (1)
        4. 8.10.3.4 Typical Interface Protocol Diagram (Slave Mode)
      4. 8.10.4  LVDS Interface Configuration
        1. 8.10.4.1 LVDS Interface Timings
      5. 8.10.5  General-Purpose Input/Output
        1. 8.10.5.1 Switching Characteristics for Output Timing versus Load Capacitance (CL) (1) (1)
      6. 8.10.6  Controller Area Network - Flexible Data-rate (CAN-FD)
        1. 8.10.6.1 Dynamic Characteristics for the CANx TX and RX Pins
      7. 8.10.7  Serial Communication Interface (SCI)
        1. 8.10.7.1 SCI Timing Requirements
      8. 8.10.8  Inter-Integrated Circuit Interface (I2C)
        1. 8.10.8.1 I2C Timing Requirements (1)
      9. 8.10.9  Quad Serial Peripheral Interface (QSPI)
        1. 8.10.9.1 QSPI Timing Conditions
        2. 8.10.9.2 Timing Requirements for QSPI Input (Read) Timings (1) (1)
        3. 8.10.9.3 QSPI Switching Characteristics
      10. 8.10.10 ETM Trace Interface
        1. 8.10.10.1 ETMTRACE Timing Conditions
        2. 8.10.10.2 ETM TRACE Switching Characteristics
      11. 8.10.11 Data Modification Module (DMM)
        1. 8.10.11.1 DMM Timing Requirements
      12. 8.10.12 JTAG Interface
        1. 8.10.12.1 JTAG Timing Conditions
        2. 8.10.12.2 Timing Requirements for IEEE 1149.1 JTAG
        3. 8.10.12.3 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Subsystems
      1. 9.3.1 RF and Analog Subsystem
        1. 9.3.1.1 Clock Subsystem
        2. 9.3.1.2 Transmit Subsystem
        3. 9.3.1.3 Receive Subsystem
      2. 9.3.2 Processor Subsystem
      3. 9.3.3 Host Interface
      4. 9.3.4 Main Subsystem Cortex-R4F
      5. 9.3.5 DSP Subsystem
      6. 9.3.6 Hardware Accelerator
    4. 9.4 Other Subsystems
      1. 9.4.1 ADC Channels (Service) for User Application
        1. 9.4.1.1 GP-ADC Parameter
  10. 10Monitoring and Diagnostics
    1. 10.1 Monitoring and Diagnostic Mechanisms
      1. 10.1.1 Error Signaling Module
  11. 11Applications, Implementation, and Layout
    1. 11.1 Application Information
    2. 11.2 Reference Schematic
  12. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Tools and Software
    3. 12.3 Documentation Support
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Packaging Information
    2. 13.2 Tray Information for ABL, 10.4 × 10.4 mm

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • ABL|161
  • ALA|209
サーマルパッド・メカニカル・データ
発注情報

9.3.1.1 Clock Subsystem

The IWR6843 clock subsystem generates 60 to 64 GHz from an input reference of 40-MHz crystal. It has a built-in oscillator circuit followed by a clean-up PLL and a RF synthesizer circuit. The output of the RF synthesizer is then processed by an X3 multiplier to create the required frequency in the 60 to 64 GHz spectrum. The RF synthesizer output is modulated by the timing engine block to create the required waveforms for effective sensor operation.

The clean-up PLL also provides a reference clock for the host processor after system wakeup.

The clock subsystem also has built-in mechanisms for detecting the presence of a crystal and monitoring the quality of the generated clock.

Figure 9-2 describes the clock subsystem.

GUID-59B76DE7-B1AD-4F7C-83D0-558180DB5143-low.gif Figure 9-2 Clock Subsystem