SNVS188I May   2004  – October 2017 LM2623


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration And Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Gated Oscillator Control Scheme.
      2. 7.3.2 Cycle-To-Cycle Pfm
      3. 7.3.3 Shutdown
      4. 7.3.4 Internal Current Limit And Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Pulse Frequency Modulation (Pfm)
      2. 7.4.2 Low Voltage Start-Up
  8. Applications And Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. Non-Linear Effect
        2. Choosing The Correct C3 Capacitor
        3. Setting The Output Voltage
        4. VDD Supply
        5. Setting The Switching Frequency
        6. Output Diode Selection
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Boost Output Capacitor Placement
      2. 10.1.2 Schottky Diode Placement
      3. 10.1.3 Boost Input / VDD Capacitor Placement
    2. 10.2 Layout Example
    3. 10.3 WSON Package Devices
  11. 11Device And Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, And Orderable Information




Layout Guidelines

The example layouts below follow proper layout guidelines and should be used as a guide for laying out the LM2623 circuit. The LM2623 inductive boost converter sees a high switched voltage at the SW pin, and a step current through the Schottky diode and output capacitor each switching cycle. The high switching voltage can create interference into nearby nodes due to electric field coupling (I = C x dV/dt). The large step current through the diode and the output capacitor can cause a large voltage spike at the SW and BOOST pins due to parasitic inductance in the step current conducting path (V = L x di/dt). Board layout guidelines are geared towards minimizing this electric field coupling and conducted noise.

Boost Output Capacitor Placement, Schottky Diode Placement, and Boost Input / VDD Capacitor Placement detail the main (layout sensitive) areas of the LM2623 inductive boost converter in order of decreasing importance:

Boost Output Capacitor Placement

Because the output capacitor is in the path of the inductor current discharge path, it will see a high-current step from 0 to IPEAK each time the switch turns off and the Schottky diode turns on. Any inductance along this series path from the diodes cathode, through COUT, and back into the LM2623 GND pin will contribute to voltage spikes at SW. These spikes can potentially over-voltage the SW and BOOST pins, or feed through to GND. To avoid this, COUT+ must be connected as close as possible to the cathode of the Schottky diode, and COUT− must be connected as close as possible to the LM2623 GND bumps. The best placement for COUT is on the same layer as the LM2623 to avoid any vias that can add excessive series inductance.

Schottky Diode Placement

In the LM2623 device boost circuit the Schottky diode is in the path of the inductor current discharge. As a result the Schottky diode sees a high-current step from 0 to IPEAK each time the switch turns off, and the diode turns on. Any inductance in series with the diode will cause a voltage spike at SW. This can potentially over-voltage the SW pin, or feed through to VOUT and through the output capacitor, into GND. Connecting the anode of the diode as close as possible to the SW pin, and connecting the cathode of the diode as close as possible to COUT+, will reduce the inductance (LP_) and minimize these voltage spikes.

Boost Input / VDD Capacitor Placement

The LM2623 input capacitor filters the inductor current ripple and the internal MOSFET driver currents. The inductor current ripple can add input voltage ripple due to any series resistance in the input power path. The MOSFET driver currents can add voltage spikes on the input due to the inductance in series with the VIN/VDD and the input capacitor. Close placement of the input capacitor to the VDD pin and to the GND pin is critical since any series inductance between VIN/VDD and CIN+ or CIN– and GND can create voltage spikes that could appear on the VIN/VDD supply line and GND.

Layout Example

LM2623 layout_snvs188.gif

WSON Package Devices

The LM2623 is offered in the 14-lead WSON surface mount package to allow for increased power dissipation compared to the VSSOP-8. For details of the thermal performance as well as mounting and soldering specifications, refer to Application Note AN-1187 Leadless Leadframe Package (LLP) (SNOA401).