JAJSFS7B July   2018  – February  2019 LM5180-Q1

ADVANCE INFORMATION for pre-production products; subject to change without notice.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーション
      2.      標準的な効率、VOUT = 5V
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Integrated Power MOSFET
      2. 8.3.2  PSR Flyback Modes of Operation
      3. 8.3.3  Setting the Output Voltage
        1. 8.3.3.1 Diode Thermal Compensation
      4. 8.3.4  Control Loop Error Amplifier
      5. 8.3.5  Precision Enable
      6. 8.3.6  Configurable Soft Start
      7. 8.3.7  External Bias Supply
      8. 8.3.8  Minimum On-Time and Off-Time
      9. 8.3.9  Overcurrent Protection
      10. 8.3.10 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Active Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design 1: Wide VIN, Low IQ PSR Flyback Converter Rated at 5 V, 1 A
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1  Custom Design With WEBENCH® Tools
          2. 9.2.1.2.2  Custom Design With Excel Quickstart Tool
          3. 9.2.1.2.3  Flyback Transformer – T1
          4. 9.2.1.2.4  Flyback Diode – DFLY
          5. 9.2.1.2.5  Clamp Circuit – DF, DCLAMP
          6. 9.2.1.2.6  Output Capacitor – COUT
          7. 9.2.1.2.7  Input Capacitor – CIN
          8. 9.2.1.2.8  Feedback Resistor – RFB
          9. 9.2.1.2.9  Thermal Compensation Resistor – RTC
          10. 9.2.1.2.10 UVLO Resistors – RUV1, RUV2
          11. 9.2.1.2.11 Soft-Start Capacitor – CSS
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Design 2: PSR Flyback Converter With Dual Outputs of 15 V and –7.7 V at 200 mA
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Flyback Transformer – T1
          2. 9.2.2.2.2 Flyback Diodes – DFLY1 and DFLY2
          3. 9.2.2.2.3 Input Capacitor – CIN
          4. 9.2.2.2.4 Feedback Resistor – RFB
          5. 9.2.2.2.5 UVLO Resistors – RUV1, RUV2
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Design 3: PSR Flyback Converter With Stacked Dual Outputs of 24 V and 5 V
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
          1. 9.2.3.2.1 Flyback Transformer – T1
          2. 9.2.3.2.2 Feedback Resistor – RFB
          3. 9.2.3.2.3 UVLO Resistors – RUV1, RUV2
        3. 9.2.3.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 12.1.2 開発サポート
      3. 12.1.3 WEBENCH® ツールによるカスタム設計
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

Typical values correspond to TJ = 25°C. Minimum and maximum limits aaply over the full –40°C to 150°C junction temperature range unless otherwise indicated. VIN = 24 V and VEN/UVLO = 2 V unless otherwise stated.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
ISHUTDOWN VIN shutdown current VEN/UVLO = 0 V 3 µA
IACTIVE VIN active current VEN/UVLO = 2.5 V, VRSET = 1.8 V 290 µA
IACTIVE_BIAS VIN current with BIAS connected VSS/BIAS = 6 V 25 µA
ENABLE AND INPUT UVLO
VSD-RISING Standby threshold VEN/UVLO rising 0.65 1.1 V
VSD-FALLING Shutdown threshold VEN/UVLO falling 0.3 V
VUV-RISING Enable threshold VEN/UVLO rising 1.47 1.5 1.53 V
IUV-HYST Enable current hysteresis VEN/UVLO = 1.6 V 5 µA
VUV-HYST Enable voltage hysteresis VEN/UVLO falling 0.05 V
FEEDBACK
IRSET RSET current RRSET = 12.1 kΩ 100 µA
VRSET RSET regulation voltage RRSET = 12.1 kΩ 1.198 1.21 1.222 V
VFB-VIN1 FB to VIN voltage IFB = 80 µA –40 mV
VFB-VIN2 FB to VIN voltage IFB = 120 µA 40 mV
SWITCHING FREQUENCY
FSW-MIN Minimum switching frequency 10 kHz
FSW-MAX Maximum switching frequency 350 kHz
tON-MIN Minimum switch on-time 150 ns
DIODE THERMAL COMPENSATION
VTC TC voltage ITC = ±10 µA, TJ = 25°C 1.2 V
POWER SWITCHES
RDS(on) MOSFET on-state resistance ISW = 100 mA 0.35 Ω
SOFT-START AND BIAS
ISS SS ext capacitor charging current 5 µA
tSS Internal SS time 6 ms
VBIAS-UVLO-RISE BIAS enable voltage VSS/BIAS rising 5.68 5.9 V
VBIAS-UVLO-HYST BIAS UVLO hysteresis VSS/BIAS falling 180 mV
CURRENT LIMIT
IPEAK Peak current limit threshold 1.35 1.5 1.65 A
THERMAL SHUTDOWN
TSD Thermal shutdown threshold TJ rising 180 °C
TSD-HYS Thermal shutdown hysteresis 20 °C