SNAS474H April   2009  – March 2015 LM98725

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Electrical Characteristics
    5. 6.5 AC Timing Specifications
    6. 6.6 Serial Interface Timing Details
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
      1. 7.2.1 LM98725 Overall Chip Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Modes of Operation Introduction
      2. 7.3.2  Mode 3 - Three Channel Input/Synchronous Pixel Sampling
      3. 7.3.3  Mode 2 - Two Channel Input/Synchronous Pixel Sampling
      4. 7.3.4  Mode 1 - One Channel Input
      5. 7.3.5  CIS Lamp and Coefficient Modes
      6. 7.3.6  Clock Sources
        1. 7.3.6.1 User Provided Clock Signal
        2. 7.3.6.2 Crystal Oscillator Driver On-Chip
        3. 7.3.6.3 Clock Multiplication - Basic
        4. 7.3.6.4 Clock Multiplication - Flexible
      7. 7.3.7  Clock Sources - Additional Settings and Flexibility
      8. 7.3.8  Spread Spectrum Clock Generation (SSCG)
      9. 7.3.9  Typical EMI Cases and Recommended SSCG Settings
      10. 7.3.10 Recommended Master/Slave, Clock Source and SSCG Combinations and Settings
        1. 7.3.10.1 Master Mode Operation (LM98725 Controls Line Timing)
        2. 7.3.10.2 Slave Mode Operation (Host FPGA or ASIC Controls Line Timing)
        3. 7.3.10.3 SSCG Configuration/Usage Flow
        4. 7.3.10.4 Changing SSCG Settings
    4. 7.4 Device Functional Modes
      1. 7.4.1  Mode 3 - Three Channel Input/Synchronous Pixel Sampling
      2. 7.4.2  Mode 2 - Two Channel Input/Synchronous Pixel Sampling
      3. 7.4.3  Mode 1 - One Channel Input
      4. 7.4.4  Input Bias and Clamping
        1. 7.4.4.1 Input Bias and Clamping - AC Coupled Applications
      5. 7.4.5  Sample/Hold Mode
      6. 7.4.6  DC Coupled Applications
      7. 7.4.7  Input Source Follower Buffers
      8. 7.4.8  CDS Mode
      9. 7.4.9  VCLP DAC
      10. 7.4.10 Gain and Offset Correction
        1. 7.4.10.1 Analog Offset
        2. 7.4.10.2 Digital Offset
        3. 7.4.10.3 Even/Odd Offset Coefficients
      11. 7.4.11 LM98725 Typical Line Timing and Pixel Gain Regions
      12. 7.4.12 Automatic Black and White Level Calibration Loops
        1. 7.4.12.1 Calibration Overview
        2. 7.4.12.2 Different Modes for Different Needs
        3. 7.4.12.3 Calibration Initiation
        4. 7.4.12.4 Key Calibration Settings
        5. 7.4.12.5 General Black Loop Operation
        6. 7.4.12.6 ADAC/DDAC Convergence
        7. 7.4.12.7 General White Loop Operation
        8. 7.4.12.8 White Loop Modes
        9. 7.4.12.9 Bimodal (Automatic) Correction
      13. 7.4.13 Coarse Pixel Phase Alignment
      14. 7.4.14 Internal Sample Timing
        1. 7.4.14.1 CCD Timing Generation
          1. 7.4.14.1.1 CCD Timing Generation
        2. 7.4.14.2 SH Interval Details - Multiple States Defined within SH Interval
        3. 7.4.14.3 SH Outputs - Low Speed Line Timing Usage
        4. 7.4.14.4 Controlled Inversion
      15. 7.4.15 CCD Timing Generator Master/Slave Modes
        1. 7.4.15.1 Master Timing Generator Mode
        2. 7.4.15.2 Slave Timing Generator Mode
        3. 7.4.15.3 Multiple SH Intervals
        4. 7.4.15.4 Support for CIS Sensors
        5. 7.4.15.5 LVDS Output Format - LM98714 Mode
      16. 7.4.16 LVDS Control Bit Coding - LM98714 Mode
        1. 7.4.16.1 Latency Compensation of CB Bits
      17. 7.4.17 Flexible LVDS Formatting Mode: Mapping
        1. 7.4.17.1 TXOUT0 Disable
        2. 7.4.17.2 Parity
        3. 7.4.17.3 Latency Compensation of CB Bits
      18. 7.4.18 LVDS Data Randomization for EMI Reduction
        1. 7.4.18.1 Mode 00: Scrambler Disabled
        2. 7.4.18.2 Mode 01: Full Scrambler Using the full 21-bit Pseudo Random Sequence
        3. 7.4.18.3 Mode 10: One Bit Scrambler Using the PRS Shift Bit Only, Sending This Bit Out on a CB Bit
        4. 7.4.18.4 Mode 11: “LSB” Scrambler
        5. 7.4.18.5 Scrambler Inhibit Bit Select
      19. 7.4.19 LVDS Drive Strength Adjust
      20. 7.4.20 LVDS Output Timing Details
        1. 7.4.20.1 Optional TXCLK Delay
      21. 7.4.21 LVDS Data Latency Diagrams
      22. 7.4.22 Data Test Patterns
        1. 7.4.22.1 LVDS Output Pattern Modes
          1. 7.4.22.1.1 Worst Case Transitions (Alternating 0x2A/0x55 on Each LVDS Pair)
          2. 7.4.22.1.2 Fixed Output Data
        2. 7.4.22.2 AFE Output Pattern Modes
          1. 7.4.22.2.1 Up-Counter Data
          2. 7.4.22.2.2 Fixed AFE Pattern
      23. 7.4.23 CMOS Output Format
      24. 7.4.24 CMOS Output Data Latency Diagrams
      25. 7.4.25 Serial Interface
        1. 7.4.25.1 Serial Interface Operating Modes
        2. 7.4.25.2 Serial Interface in Absence of MCLK
        3. 7.4.25.3 Writing to the Serial Registers
        4. 7.4.25.4 Reading the Serial Registers
        5. 7.4.25.5 LM98714 Compatible 3 Wire Serial Signaling
    5. 7.5 Register Maps
      1. 7.5.1 Configuration Registers
        1. 7.5.1.1 Register Summary Table
  8. 8 Layout
    1. 8.1 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Trademarks
    2. 9.2 Device Support
    3. 9.3 Electrostatic Discharge Caution
    4. 9.4 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9 Device and Documentation Support

9.1 Trademarks

All other trademarks are the property of their respective owners.

9.2 Device Support

For additional information, see Texas Instruments' E2E community resources: http://e2e.ti.com.

9.3 Electrostatic Discharge Caution

esds-image

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

9.4 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.