JAJSER7D November   2018  – January 2019 LMG1210

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーションの概略図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
    8. 7.8 Timing Diagrams
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Bootstrap Diode Operation
      2. 8.3.2 LDO Operation
      3. 8.3.3 Dead Time Selection
      4. 8.3.4 Overtemperature Protection
      5. 8.3.5 High-Performance Level Shifter
      6. 8.3.6 Negative HS Voltage Handling
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Bypass Capacitor
        2. 9.2.2.2 Bootstrap Diode Selection
        3. 9.2.2.3 Handling Ground Bounce
        4. 9.2.2.4 Independent Input Mode
        5. 9.2.2.5 Computing Power Dissipation
      3. 9.2.3 Application Curves
    3. 9.3 Do's and Don'ts
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
  • RVR|19
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

VDD=5V, HB-HS=4.6V, outputs unloaded over operating junction temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
IDD Quiescent Current for Low-Side Circuits Only,  Vin=6V, powered through LDO LI, HI=0V, Independent Mode 300 475 μA
EN=0V, PWM=X, PWM Input Mode, RDHL and RDLH = 1.78MΩ 380 550 μA
IHB HB Quiescent Current HI=0V, Independent Mode 520 850 μA
IHBS HB to VSS Quiescent Current VHS=100V 1 nA
IHBSO HB to VSS Operating Current VHS=100V, FSW=1MHz 1 nA
ILSDyn Low-side dynamic current Unloaded, PWM Mode 1 1.25 mA/MHz
IHSDyn High-side dynamic current Unloaded 0.5 0.7 mA/MHz
LOW-SIDE TO HIGH-SIDE CAPACITANCE
CISO Capacitance from High to Low Side Low Side Pins Shorted Together, High Side Pins Shorted Together 0.25 pF
5V LDO
V5V LDO Output VIN=10V 4.75 5.00 5.25 V
VDO Dropout Voltage IO=100mA 400 750 mV
ILDOM Maximum Current VIN=12V 100 mA
ISC Short Circuit Current VIN=12V 105 250 mA
COUT Minimum Required Output Capacitance(2) Effective Capacitance at Bias Voltage 0.3 µF
DIGITAL INPUT PINS (LI/PWM & HI/EN)
VIR Input Rising Edge Threshold 1.70 2.45 V
VIF Input Falling Edge Threshold 0.70 1.30 V
VIHYS Input Hysteresis 1 V
RIPD Input Pull-Down Resistance VLI, VHI=1V 100 200 300 kΩ
UNDERVOLTAGE LOCKOUT
VDDR VDD Rising Threshold 4.00 4.25 4.50 V
VDDF VDD Falling Threshold 3.8 4.05 4.3 V
VDDH VDD Hysteresis 200 mV
VHBR HB-HS Rising Threshold 3.40 3.55 3.8 V
VHBF HB-HS Falling Threshold 3.30 3.45 3.65 V
VHBH HB-HS Hysteresis 130 mV
BOOTSTRAP DIODE SWITCH
RSW Diode Switch On Resistance ID=100mA 0.4 Ω
GATE DRIVER
VOL Low-Level Output Voltage IOL=100mA 0.16 V
VDD-VOH High-Level Output Voltage IOH= -100mA 0.30 V
IOL Peak Sink Current VLO,VHO=5V 2.0 3.1 4.3 A
IOH Peak Source Current VLO,VHO=0V 0.85 1.58 2.4 A
VCLAMP Unpowered Gate Clamp Voltage VDD, VHB Floating, 1 mA pull-up applied to LO/HO 0.55 0.8 V
THERMAL SHUTDOWN
TSD Thermal Shutdown Switching, Rising Edge(1) 150 °C
TSD_LDO Thermal Shut Down LDO, Rising Edge(1) 160 °C
THYS_SD Thermal Hysteresis, LDO & Switching(1) 3 10 °C
TSD_HS Thermal Shutdown for High-Side, Rising Edge(1) 160 °C
DEADTIME CONTROL RESISTORS
RPU Internal Pullup Resistor 23.5 25 27 kΩ
(1) Ensured by design
(2) Ensured by design