JAJSER7D November   2018  – January 2019 LMG1210

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーションの概略図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
    8. 7.8 Timing Diagrams
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Bootstrap Diode Operation
      2. 8.3.2 LDO Operation
      3. 8.3.3 Dead Time Selection
      4. 8.3.4 Overtemperature Protection
      5. 8.3.5 High-Performance Level Shifter
      6. 8.3.6 Negative HS Voltage Handling
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Bypass Capacitor
        2. 9.2.2.2 Bootstrap Diode Selection
        3. 9.2.2.3 Handling Ground Bounce
        4. 9.2.2.4 Independent Input Mode
        5. 9.2.2.5 Computing Power Dissipation
      3. 9.2.3 Application Curves
    3. 9.3 Do's and Don'ts
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
  • RVR|19
サーマルパッド・メカニカル・データ
発注情報

8.3.1 Bootstrap Diode Operation

An internal low impedance switch enables the bootstrap only when the low-side GaN FET is on. If used in a converter where the low-side FET operates in third quadrant conduction during the dead times, this provides two main benefits. First, it stops the bootstrap diode from overcharging the high-side bootstrap rail. Second, if using a p-n junction diode with Qrr as the bootstrap diode, it decreases the Qrr losses of the diode. There is a 1 kΩ resistor connected between the drain and source of this internal bootstrap switch to allow the bootstrap capacitor to slowly charge at start-up before the low-side FET is turned on.

The part does not have an actual clamp on the high-side bootstrap supply. The bootstrap switch disables conduction during the dead times, and the actual bootstrap capacitor voltage is set by the operating conditions of the circuit during the low-side on-time. The bootstrap voltage can be approximately calculated in Equation 1 through Equation 3.

The bootstrap voltage is given by Equation 1:

Equation 1. VBST = VDD – VF – VHS

where

  • VF is the forward voltage drop of the bootstrap diode and series bootstrap switch.

VHS is calculated in Equation 2:

Equation 2. VHS = –IL × RDSON

where

  • IL is the inductor current defined as flowing out of the half-bridge
  • and RDSON is the FET on resistance.

Substituting (2) into (1) gives the expression for the bootstrap voltage as Equation 3:

Equation 3. VBST = VDD – VF + IL × RDSON

From (3) one can determine that in an application where the current flows out of the half-bridge (IL is positive) the bootstrap voltage can be charged up to a voltage higher than VDD if IL × RDSON is greater than VF. Take care not to overcharge the bootstrap too much in this application by choosing a diode with a larger VF or limiting the IL × RDSON product.

In an application where IL is negative, the IL × RDSON product subtracts from the available bootstrap cap voltage. In this case using a smaller VF diode is recommended if IL × RDSON is large.