JAJSL98B October   2020  – June 2021 LMG3522R030-Q1 , LMG3525R030-Q1

ADVANCE INFORMATION  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Device Comparison
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
  8. Parameter Measurement Information
    1. 8.1 Switching Parameters
      1. 8.1.1 Turn-On Delays
      2. 8.1.2 Turn-Off Delays
      3. 8.1.3 Drain Slew Rate
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Direct-Drive GaN Architecture
      2. 9.3.2 Drain-Source Voltage Capability
      3. 9.3.3 Internal Buck-Boost DC-DC Converter
      4. 9.3.4 VDD Bias Supply
      5. 9.3.5 Auxiliary LDO
      6. 9.3.6 Fault Detection
        1. 9.3.6.1 Overcurrent Protection and Short-Circuit Protection
        2. 9.3.6.2 Overtemperature Shutdown
        3. 9.3.6.3 UVLO Protection
        4. 9.3.6.4 Fault Reporting
      7. 9.3.7 Drive Strength Adjustment
      8. 9.3.8 Temperature-Sensing Output
      9. 9.3.9 Sync-FET Mode Operation
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Slew Rate Selection
          1. 10.2.2.1.1 Start-Up and Slew Rate With Bootstrap High-Side Supply
        2. 10.2.2.2 Signal Level-Shifting
        3. 10.2.2.3 Buck-Boost Converter Design
    3. 10.3 Do's and Don'ts
  11. 11Power Supply Recommendations
    1. 11.1 Using an Isolated Power Supply
    2. 11.2 Using a Bootstrap Diode
      1. 11.2.1 Diode Selection
      2. 11.2.2 Managing the Bootstrap Voltage
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Power Loop Inductance
      2. 12.1.2 Signal Ground Connection
      3. 12.1.3 Bypass Capacitors
      4. 12.1.4 Switch-Node Capacitance
      5. 12.1.5 Signal Integrity
      6. 12.1.6 High-Voltage Spacing
      7. 12.1.7 Thermal Recommendations
    2. 12.2 Layout Examples
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 サポート・リソース
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Export Control Notice
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information
    1. 14.1 Tape and Reel Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ(パッケージ|ピン)
  • RQS|52
サーマルパッド・メカニカル・データ
発注情報

Pin Configuration and Functions

Figure 6-1 RQS (VQFN) Package52 Pins(Top View)
Table 6-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
LDO5V 51 P 5-V LDO output for external digital isolator.
RDRV 50 I Drive strength selection pin. Connect a resistor from this pin to ground to set the turn-on drive strength to control slew rate. Tie the pin to GND to enable 150 V/ns and tie the pin to LDO5V to enable 100 V/ns.
TEMP 49 O Temperature-sensing output.
OC 48 O Overcurrent and short-circuit fault output, push-pull, active low. Refer to Section 9.3.6 for details.
FAULT 46 O Fault output, push-pull, active low. Refer to Section 9.3.6 for details.
IN 45 I CMOS-compatible noninverting gate drive input.
VDD 44 P 12-V power input, relative to source. Supplies 5-V rail and gate drive supply.
BBSW 42 P Internal buck-boost converter switch pin. Connect an inductor from this point to power ground.
VNEG 40, 41 P Negative supply output, bypass to ground with ceramic capacitors.
SOURCE 18-26, 28-39 P Power transistor source, die-attach pad, thermal sink, power ground.
NU 17, 27, 43, 47, 52 NU These pins must be soldered onto the PCB’s landing pads. The PCB’s landing pads are non-solder mask defined pads and not to be electrically connected to any electrical signals on the PCB. The pins are electrically connected internally to the SOURCE of the power device.
DRAIN 2-15 P Power transistor drain.
NU 1, 16 NU These pins must be soldered onto the PCB’s landing pads. The PCB’s landing pads are non-solder mask defined pads and not to be electrically connected to any electrical signals on the PCB. The pins are electrically connected internally to the DRAIN of the power device.
Thermal Pad Thermal pad on top (Internally connected to SOURCE).
I = input, O = output, P = power, NU = make no external connection