JAJSL98B October   2020  – June 2021 LMG3522R030-Q1 , LMG3525R030-Q1

ADVANCE INFORMATION  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Device Comparison
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
  8. Parameter Measurement Information
    1. 8.1 Switching Parameters
      1. 8.1.1 Turn-On Delays
      2. 8.1.2 Turn-Off Delays
      3. 8.1.3 Drain Slew Rate
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Direct-Drive GaN Architecture
      2. 9.3.2 Drain-Source Voltage Capability
      3. 9.3.3 Internal Buck-Boost DC-DC Converter
      4. 9.3.4 VDD Bias Supply
      5. 9.3.5 Auxiliary LDO
      6. 9.3.6 Fault Detection
        1. 9.3.6.1 Overcurrent Protection and Short-Circuit Protection
        2. 9.3.6.2 Overtemperature Shutdown
        3. 9.3.6.3 UVLO Protection
        4. 9.3.6.4 Fault Reporting
      7. 9.3.7 Drive Strength Adjustment
      8. 9.3.8 Temperature-Sensing Output
      9. 9.3.9 Sync-FET Mode Operation
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Slew Rate Selection
          1. 10.2.2.1.1 Start-Up and Slew Rate With Bootstrap High-Side Supply
        2. 10.2.2.2 Signal Level-Shifting
        3. 10.2.2.3 Buck-Boost Converter Design
    3. 10.3 Do's and Don'ts
  11. 11Power Supply Recommendations
    1. 11.1 Using an Isolated Power Supply
    2. 11.2 Using a Bootstrap Diode
      1. 11.2.1 Diode Selection
      2. 11.2.2 Managing the Bootstrap Voltage
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Power Loop Inductance
      2. 12.1.2 Signal Ground Connection
      3. 12.1.3 Bypass Capacitors
      4. 12.1.4 Switch-Node Capacitance
      5. 12.1.5 Signal Integrity
      6. 12.1.6 High-Voltage Spacing
      7. 12.1.7 Thermal Recommendations
    2. 12.2 Layout Examples
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 サポート・リソース
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Export Control Notice
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information
    1. 14.1 Tape and Reel Information

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発注情報

Sync-FET Mode Operation

GaN devices do not have body diodes, but is still able to conduct current in third-quadrant (source to drain) when it is OFF. However, the voltage drop of GaN devices is higher than that of Si diodes during third-quadrant conduction. This results in higher power loss if not handled properly. The excessive loss can be observed in prolonged dead time or cycle-by-cycle current limit mode, leading to overtemperature, which could trigger protective shut down. To mitigate this problem, a Sync-FET Mode operation is implemented in the power IC.

Figure 9-5 shows how Sync-FET Mode operation achieves adaptive dead time and reduces third-quadrant loss in a boost converter. Before IN Pin of the free-wheeling IC goes high, the IC is able to detect the third-quadrant current and automatically turn ON GaN device after td(idm_on), typically around 35ns. When IN Pin of the free-wheeling IC goes low, GaN device is turned OFF. After turn-off transient, there is a blanking time, t3rd_Blank, typically around 115ns, to prevent the unwanted re-turn on during dead time.

A state machine has been also used to summarize the Sync-FET Mode operation. Please see Figure 9-6. In a half bridge:

  • For the hard-switching IC in a half bridge
    • When IN Pin goes high, GaN device is always turned ON, and the hard-switching IC starts conducting first-quadrant current.
    • When IN Pin goes low, GaN device is turned OFF, and the hard-switching IC starts blocking positive VDS.
    • When t3rd_Blank expires, GaN device stays OFF, and the hard-switching IC starts detecting first-quadrant current, including both conduction and leakage current.
    • When leakage current and positive VDS presents, GaN device stays OFF and keeps blocking before IN Pin of the hard-switching IC goes high.
  • For the free-wheeling IC in a half bridge
    • When IN Pin goes high, GaN device is always turned ON, and the free-wheeling IC starts conducting third-quadrant current at negative VDS, product of negative ID and RDS(on).
    • When IN Pin goes low, GaN device is turned OFF, and the free-wheeling IC starts conducting third-quadrant current at VSD, third-quadrant mode source-drain voltage.
    • When t3rd_Blank expires, GaN device stays OFF and continues third-quadrant conduction, and the free-wheeling IC starts detecting first-quadrant current, including both conduction and leakage current.
    • When first-quadrant current and positive VDS presents at turn ON of the hard-switching IC, GaN device stays OFF but starts blocking, and the free-wheeling IC starts detecting third-quadrant current.
    • When third-quadrant current and negative VDS presents at turn OFF of the hard switching IC, GaN device stays OFF during detection, t3rd_Det, and then is turned ON by Sync-FET Mode. In Sync-FET Mode, the free-wheeling IC keeps detecting first-quadrant current, including both conduction and leakage current, before IN Pin goes high.
    • If first-quadrant current presents before IN Pin goes high, GaN device will be turned OFF, and the free-wheeling IC will NOT be turned ON again by Sync-FET Mode before IN Pin goes high.

Figure 9-5 Dead Time Reduction In Sync Mode Operation
GUID-626B32FD-529A-42DA-8B78-8197D7614614-low.gif Figure 9-6 Sync FET Mode State Machine