The power loop, comprising the two devices in the half bridge and the high-voltage bus capacitance, undergoes high di/dt during switching events. By minimizing the inductance of this loop, ringing and electro-magnetic interference (EMI) can be reduced, as well as reducing voltage stress on the devices.
Place the power devices as close as possible to minimize the power loop inductance. The decoupling capacitors are positioned in line with the two devices. They can be placed close to either device. In Section 12.2, the devices are placed on the bottom layer and the decoupling capacitors are placed on top layer. The PGND is placed on top layer, the HVBUS is located on top and third layer, and the switching node is on top layer. They are connected to the power devices on bottom layer with vias. Area of traces close to the devices are minimized at bottom layer in order to keep clearance between heatsink and conductors.