JAJSL98B October   2020  – June 2021 LMG3522R030-Q1 , LMG3525R030-Q1

ADVANCE INFORMATION  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Device Comparison
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
  8. Parameter Measurement Information
    1. 8.1 Switching Parameters
      1. 8.1.1 Turn-On Delays
      2. 8.1.2 Turn-Off Delays
      3. 8.1.3 Drain Slew Rate
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Direct-Drive GaN Architecture
      2. 9.3.2 Drain-Source Voltage Capability
      3. 9.3.3 Internal Buck-Boost DC-DC Converter
      4. 9.3.4 VDD Bias Supply
      5. 9.3.5 Auxiliary LDO
      6. 9.3.6 Fault Detection
        1. 9.3.6.1 Overcurrent Protection and Short-Circuit Protection
        2. 9.3.6.2 Overtemperature Shutdown
        3. 9.3.6.3 UVLO Protection
        4. 9.3.6.4 Fault Reporting
      7. 9.3.7 Drive Strength Adjustment
      8. 9.3.8 Temperature-Sensing Output
      9. 9.3.9 Sync-FET Mode Operation
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Slew Rate Selection
          1. 10.2.2.1.1 Start-Up and Slew Rate With Bootstrap High-Side Supply
        2. 10.2.2.2 Signal Level-Shifting
        3. 10.2.2.3 Buck-Boost Converter Design
    3. 10.3 Do's and Don'ts
  11. 11Power Supply Recommendations
    1. 11.1 Using an Isolated Power Supply
    2. 11.2 Using a Bootstrap Diode
      1. 11.2.1 Diode Selection
      2. 11.2.2 Managing the Bootstrap Voltage
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Power Loop Inductance
      2. 12.1.2 Signal Ground Connection
      3. 12.1.3 Bypass Capacitors
      4. 12.1.4 Switch-Node Capacitance
      5. 12.1.5 Signal Integrity
      6. 12.1.6 High-Voltage Spacing
      7. 12.1.7 Thermal Recommendations
    2. 12.2 Layout Examples
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 サポート・リソース
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Export Control Notice
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information
    1. 14.1 Tape and Reel Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ(パッケージ|ピン)
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発注情報

Switching Characteristics

Unless otherwise noted: voltage, resistance, capacitance, and inductance are respect to SOURCE connected with reference ground; –40 ℃ ≤ TJ ≤ 125 ℃; 9 V ≤ VVDD ≤ 18 V; VIN = 5 V; RDRV connected to LDO5V;  LBBSW = 4.7 µH
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SWITCHING TIMES
tpd(on) Driver turn-on propagation delay From VIN > VIN,IT+ to ID > 1 A, VBUS = 400 V, LHB current = 10 A, see Figure 8-1 and Figure 8-2 30 50 ns
td(on) Turn-on delay From ID > 1 A to VDS < 320 V, VBUS = 400 V, LHB current = 10 A, see Figure 8-1 and Figure 8-2 5 6 ns
tr(on) Turn-on rise time From VDS < 320 V to VDS < 80 V, VBUS = 400 V, LHB current = 10 A, see Figure 8-1 and Figure 8-2 2.5 3 ns
tpd(off) Driver turn-off propagation delay From VIN < VIN,IT– to VDS > 10 V, VBUS = 400 V, LHB current = 10 A, see Figure 8-1 and Figure 8-2 32 50 ns
td(off) Turn-off delay From VDS > 10 V to VDS > 80 V, VBUS = 400 V, LHB current = 10 A, see Figure 8-1 and Figure 8-2 6 10 ns
tf(off) Turn-off fall time(1) From VDS > 80 V to VDS > 320 V, VBUS = 400 V, LHB current = 10 A, see Figure 8-1 and Figure 8-2 23 ns
Minimum IN high pulse-width for FET turn-on VIN rise/fall times < 1 ns, VDS falls to < 200 V, VBUS = 400 V, LHB current = 10 A, see Figure 8-1 24 ns
STARTUP TIMES
Driver start-up delay time From VVDD > VVDD,IT+(UVLO) to /FAULT high, CLDO5V = 100 nF, CVNEG = 2.2 µF at 0-V bias linearly decreasing to 1.5 µF at 15-V bias 400 us
FAULT TIMES
td(OC) Overcurrent fault FET turn-off delay, FET on before overcurrent From ID > IIT(OC) to FET off, ID di/dt = 100 A/µs 90 135 ns
td(SC) Short-circuit current fault FET turn-off delay, FET on before short circuit From ID > IIT(SC) to FET off, ID di/dt = 700 A/µs 90 135 ns
Overcurrent fault FET turn-off delay, FET turning on into overcurrent From FET turn-on to FET off, dv/dt = 100 V/ns 200 280 ns
Short-circuit fault FET turn-off delay, FET turning on into short circuit From FET turn-on to FET off, dv/dt = 100 V/ns 105 217 ns
td(reset) IN reset delay time to clear /FAULT latch From VIN < VIN,IT– to /FAULT high 250 350 580 us
THIRD QUADRANT TURN ON (LMG3525)
td(idm_on) Ideal diode mode FET turn-on delay time VDS < VIT(3rd) to FET turn-on, VDS dv/dt = –100 V/ns created with a half-bridge configuration inductor at 5 A 35 75 ns
td(idm_off) Ideal diode mode FET turn-off delay time ID > IIT(ZC) to FET turn-off, ID di/dt = 100 A/µs created with a half-bridge configuration 30 68 ns
t3rd_Blank Blanking time after IN falling for ideal-diode-mode. 80 115 180 ns
During turn off, VDS rise time is the result of the resonance of COSS and loop inductance, as well as load current.