SBOS730A April   2015  – May 2015 LMH6401

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Options
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 SPI Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Setup Diagrams
    2. 8.2 Output Measurement Reference Points
    3. 8.3 ATE Testing and DC Measurements
    4. 8.4 Frequency Response
    5. 8.5 Distortion
    6. 8.6 Noise Figure
    7. 8.7 Pulse Response, Slew Rate, and Overdrive Recovery
    8. 8.8 Power Down
    9. 8.9 VOCM Frequency Response
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
      1. 9.4.1 Power-On Reset (POR)
      2. 9.4.2 Power-Down (PD)
      3. 9.4.3 Thermal Feedback Control
      4. 9.4.4 Gain Control
    5. 9.5 Programming
      1. 9.5.1 Details of the Serial Interface
      2. 9.5.2 Timing Diagrams
    6. 9.6 Register Maps
      1. 9.6.1 Revision ID (address = 0h, Read-Only) [default = 03h]
      2. 9.6.2 Product ID (address = 1h, Read-Only) [default = 00h]
      3. 9.6.3 Gain Control (address = 2h) [default = 20h]
      4. 9.6.4 Reserved (address = 3h) [default = 8Ch]
      5. 9.6.5 Thermal Feedback Gain Control (address = 4h) [default = 27h]
      6. 9.6.6 Thermal Feedback Frequency Control (address = 5h) [default = 45h]
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Analog Input Characteristics
      2. 10.1.2 Analog Output Characteristics
        1. 10.1.2.1 Driving Capacitive Loads
      3. 10.1.3 Thermal Feedback Control
        1. 10.1.3.1 Step Response Optimization using Thermal Feedback Control
      4. 10.1.4 Thermal Considerations
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Driving ADCs
          1. 10.2.2.1.1 SNR Considerations
          2. 10.2.2.1.2 SFDR Considerations
          3. 10.2.2.1.3 ADC Input Common-Mode Voltage Considerations—AC-Coupled Input
          4. 10.2.2.1.4 ADC Input Common-Mode Voltage Considerations—DC-Coupled Input
      3. 10.2.3 Application Curves
    3. 10.3 Do's and Don'ts
      1. 10.3.1 Do:
      2. 10.3.2 Don't:
  11. 11Power-Supply Recommendations
    1. 11.1 Single-Supply Operation
    2. 11.2 Split-Supply Operation
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Examples
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

12 Layout

12.1 Layout Guidelines

When dealing with a device with relatively high gain and bandwidth in excess of 1 GHz, certain board layout precautions must be taken to ensure stability and optimum performance. TI recommends that the LMH6401 board be multi-layered to improve thermal performance, grounding, and power-supply decoupling. The differential input and output traces must be symmetrical in order to achieve the best linearity performance.

By sandwiching the power-supply layer between ground layers on either side (with thin dielectric thicknesses), parasitic capacitance between power and ground functions as a distributed, high-resonance frequency capacitor to help with power-supply decoupling. The LMH6401 evaluation board includes a total of six layers and the positive (VS+) and negative (VS–) power planes are sandwiched in the middle with a board stack-up (dielectric thickness), as shown in Figure 71, to help with supply decoupling. Both VS+ and VS– must be connected to the internal power planes through multiple vias in the immediate vicinity of the supply pins. In addition, low ESL, ceramic, 0.01-μF decoupling capacitors to the supplies are placed on the same layer as the device to provide supply decoupling.

Routing high-frequency signal traces on a PCB requires careful attention to maintain signal integrity. A board layout software package can simplify the trace thickness design to maintain impedances for controlled impedance signals. In order to isolate the affect of board parasitic on frequency response, TI recommends placing the external output matching resistors close to the amplifier output pins. A 0.01-µF bypass capacitor is also recommended close to the VOCM pins to suppress high-frequency common-mode noise. Refer to the user guide LMH6401EVM Evaluation Module (SLOU406) for more details on board layout and design.

In order to improve board mechanical reliability, the LMH6401 has square anchor pins on four corners of the package that must be soldered to the board for mechanical strength.

LMH6401 LayerStackup_sbos730.gifFigure 71. Recommended PCB Layer Stack-Up for a Six-Layer Board

12.2 Layout Examples

LMH6401 LMH6401EVM_TopLayer.gifFigure 72. EVM Top Layer
LMH6401 LMH6401EVM_SecondLayer.gifFigure 73. EVM Second Layer Showing a Solid GND Plane