SNAS605AS March   2013  – May 2020 LMK04821 , LMK04826 , LMK04828

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Simplified Schematic
  4. Revision History
  5. Device Comparison Table
    1. 5.1 Device Configuration Information
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 SPI Interface Timing
    7. 7.7 Typical Characteristics – Clock Output AC Characteristics
  8. Parameter Measurement Information
    1. 8.1 Charge Pump Current Specification Definitions
      1. 8.1.1 Charge Pump Output Current Magnitude Variation Vs. Charge Pump Output Voltage
      2. 8.1.2 Charge Pump Sink Current Vs. Charge Pump Output Source Current Mismatch
      3. 8.1.3 Charge Pump Output Current Magnitude Variation Vs. Ambient Temperature
    2. 8.2 Differential Voltage Measurement Terminology
  9. Detailed Description
    1. 9.1 Overview
      1. 9.1.1  Jitter Cleaning
      2. 9.1.2  JEDEC JESD204B Support
      3. 9.1.3  Three PLL1 Redundant Reference Inputs
      4. 9.1.4  VCXO/Crystal Buffered Output
      5. 9.1.5  Frequency Holdover
      6. 9.1.6  PLL2 Integrated Loop Filter Poles
      7. 9.1.7  Internal VCOs
        1. 9.1.7.1 VCO1 Divider (LMK04821 only)
      8. 9.1.8  External VCO Mode
      9. 9.1.9  Clock Distribution
        1. 9.1.9.1 Device Clock Divider
        2. 9.1.9.2 SYSREF Clock Divider
        3. 9.1.9.3 Device Clock Delay
        4. 9.1.9.4 SYSREF Delay
        5. 9.1.9.5 Glitchless Half Step and Glitchless Analog Delay
        6. 9.1.9.6 Programmable Output Formats
        7. 9.1.9.7 Clock Output Synchronization
      10. 9.1.10 Zero-Delay
      11. 9.1.11 Status Pins
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 SYNC/SYSREF
      2. 9.3.2 JEDEC JESD204B
        1. 9.3.2.1 How To Enable SYSREF
          1. 9.3.2.1.1 Setup of SYSREF Example
          2. 9.3.2.1.2 SYSREF_CLR
        2. 9.3.2.2 SYSREF Modes
          1. 9.3.2.2.1 SYSREF Pulser
          2. 9.3.2.2.2 Continuous SYSREF
          3. 9.3.2.2.3 SYSREF Request
      3. 9.3.3 Digital Delay
        1. 9.3.3.1 Fixed Digital Delay
          1. 9.3.3.1.1 Fixed Digital Delay Example
        2. 9.3.3.2 Dynamic Digital Delay
        3. 9.3.3.3 Single and Multiple Dynamic Digital Delay Example
      4. 9.3.4 SYSREF to Device Clock Alignment
      5. 9.3.5 Input Clock Switching
        1. 9.3.5.1 Input Clock Switching - Manual Mode
        2. 9.3.5.2 Input Clock Switching - Pin Select Mode
        3. 9.3.5.3 Input Clock Switching - Automatic Mode
      6. 9.3.6 Digital Lock Detect
      7. 9.3.7 Holdover
        1. 9.3.7.1 Enable Holdover
          1. 9.3.7.1.1 Fixed (Manual) CPout1 Holdover Mode
          2. 9.3.7.1.2 Tracked CPout1 Holdover Mode
        2. 9.3.7.2 Entering Holdover
        3. 9.3.7.3 During Holdover
        4. 9.3.7.4 Exiting Holdover
        5. 9.3.7.5 Holdover Frequency Accuracy and DAC Performance
        6. 9.3.7.6 Holdover Mode - Automatic Exit of Holdover
    4. 9.4 Device Functional Modes
      1. 9.4.1 Dual PLL
      2. 9.4.2 Zero-Delay Dual PLL
      3. 9.4.3 Single-Loop Mode
      4. 9.4.4 Single-Loop Mode With External VCO
      5. 9.4.5 Distribution Mode
    5. 9.5 Programming
      1. 9.5.1 Recommended Programming Sequence
        1. 9.5.1.1 SPI LOCK
        2. 9.5.1.2 SYSREF_CLR
        3. 9.5.1.3 RESET Pin
    6. 9.6 Register Maps
      1. 9.6.1 Register Map for Device Programming
    7. 9.7 Device Register Descriptions
      1. 9.7.1 System Functions
        1. 9.7.1.1 RESET, SPI_3WIRE_DIS
        2. 9.7.1.2 POWERDOWN
        3. 9.7.1.3 ID_DEVICE_TYPE
        4. 9.7.1.4 ID_PROD[15:8], ID_PROD
        5. 9.7.1.5 ID_MASKREV
        6. 9.7.1.6 ID_VNDR[15:8], ID_VNDR
      2. 9.7.2 (0x100 - 0x138) Device Clock and SYSREF Clock Output Controls
        1. 9.7.2.1 CLKoutX_Y_ODL, CLKoutX_Y_IDL, DCLKoutX_DIV
        2. 9.7.2.2 DCLKoutX_DDLY_CNTH, DCLKoutX_DDLY_CNTL
        3. 9.7.2.3 DCLKoutX_ADLY, DCLKoutX_ADLY_MUX, DCLKout_MUX
        4. 9.7.2.4 DCLKoutX_HS, SDCLKoutY_MUX, SDCLKoutY_DDLY, SDCLKoutY_HS
        5. 9.7.2.5 SDCLKoutY_ADLY_EN, SDCLKoutY_ADLY
        6. 9.7.2.6 DCLKoutX_DDLY_PD, DCLKoutX_HSg_PD, DCLKout_ADLYg_PD, DCLKout_ADLY_PD, DCLKoutX_Y_PD, SDCLKoutY_DIS_MODE, SDCLKoutY_PD
        7. 9.7.2.7 SDCLKoutY_POL, SDCLKoutY_FMT, DCLKoutX_POL, DCLKoutX_FMT
      3. 9.7.3 SYSREF, SYNC, and Device Config
        1. 9.7.3.1  VCO_MUX, OSCout_MUX, OSCout_FMT
        2. 9.7.3.2  SYSREF_CLKin0_MUX, SYSREF_MUX
        3. 9.7.3.3  SYSREF_DIV[12:8], SYSREF_DIV[7:0]
        4. 9.7.3.4  SYSREF_DDLY[12:8], SYSREF_DDLY[7:0]
        5. 9.7.3.5  SYSREF_PULSE_CNT
        6. 9.7.3.6  PLL2_NCLK_MUX, PLL1_NCLK_MUX, FB_MUX, FB_MUX_EN
        7. 9.7.3.7  PLL1_PD, VCO_LDO_PD, VCO_PD, OSCin_PD, SYSREF_GBL_PD, SYSREF_PD, SYSREF_DDLY_PD, SYSREF_PLSR_PD
        8. 9.7.3.8  DDLYdSYSREF_EN, DDLYdX_EN
        9. 9.7.3.9  DDLYd_STEP_CNT
        10. 9.7.3.10 SYSREF_CLR, SYNC_1SHOT_EN, SYNC_POL, SYNC_EN, SYNC_PLL2_DLD, SYNC_PLL1_DLD, SYNC_MODE
        11. 9.7.3.11 SYNC_DISSYSREF, SYNC_DISX
        12. 9.7.3.12 Fixed Registers (0x145, 0x171 - 0x172)
      4. 9.7.4 (0x146 - 0x149) CLKin Control
        1. 9.7.4.1 CLKin2_EN, CLKin1_EN, CLKin0_EN, CLKin2_TYPE, CLKin1_TYPE, CLKin0_TYPE
        2. 9.7.4.2 CLKin_SEL_POL, CLKin_SEL_MODE, CLKin1_OUT_MUX, CLKin0_OUT_MUX
        3. 9.7.4.3 CLKin_SEL0_MUX, CLKin_SEL0_TYPE
        4. 9.7.4.4 SDIO_RDBK_TYPE, CLKin_SEL1_MUX, CLKin_SEL1_TYPE
      5. 9.7.5 RESET_MUX, RESET_TYPE
      6. 9.7.6 (0x14B - 0x152) Holdover
        1. 9.7.6.1 LOS_TIMEOUT, LOS_EN, TRACK_EN, HOLDOVER_FORCE, MAN_DAC_EN, MAN_DAC[9:8]
        2. 9.7.6.2 MAN_DAC[9:8], MAN_DAC[7:0]
        3. 9.7.6.3 DAC_TRIP_LOW
        4. 9.7.6.4 DAC_CLK_MULT, DAC_TRIP_HIGH
        5. 9.7.6.5 DAC_CLK_CNTR
        6. 9.7.6.6 CLKin_OVERRIDE, HOLDOVER_PLL1_DET, HOLDOVER_LOS_DET, HOLDOVER_VTUNE_DET, HOLDOVER_HITLESS_SWITCH, HOLDOVER_EN
        7. 9.7.6.7 HOLDOVER_DLD_CNT[13:8], HOLDOVER_DLD_CNT[7:0]
      7. 9.7.7 (0x153 - 0x15F) PLL1 Configuration
        1. 9.7.7.1 CLKin0_R[13:8], CLKin0_R[7:0]
        2. 9.7.7.2 CLKin1_R[13:8], CLKin1_R[7:0]
        3. 9.7.7.3 CLKin2_R[13:8], CLKin2_R[7:0]
        4. 9.7.7.4 PLL1_N
        5. 9.7.7.5 PLL1_WND_SIZE, PLL1_CP_TRI, PLL1_CP_POL, PLL1_CP_GAIN
        6. 9.7.7.6 PLL1_DLD_CNT[13:8], PLL1_DLD_CNT[7:0]
        7. 9.7.7.7 PLL1_R_DLY, PLL1_N_DLY
        8. 9.7.7.8 PLL1_LD_MUX, PLL1_LD_TYPE
      8. 9.7.8 (0x160 - 0x16E) PLL2 Configuration
        1. 9.7.8.1 PLL2_R[11:8], PLL2_R[7:0]
        2. 9.7.8.2 PLL2_P, OSCin_FREQ, PLL2_XTAL_EN, PLL2_REF_2X_EN
        3. 9.7.8.3 PLL2_N_CAL
        4. 9.7.8.4 PLL2_FCAL_DIS, PLL2_N
        5. 9.7.8.5 PLL2_WND_SIZE, PLL2_CP_GAIN, PLL2_CP_POL, PLL2_CP_TRI
        6. 9.7.8.6 SYSREF_REQ_EN, PLL2_DLD_CNT
        7. 9.7.8.7 PLL2_LF_R4, PLL2_LF_R3
        8. 9.7.8.8 PLL2_LF_C4, PLL2_LF_C3
        9. 9.7.8.9 PLL2_LD_MUX, PLL2_LD_TYPE
      9. 9.7.9 (0x16F - 0x1FFF) Misc Registers
        1. 9.7.9.1  PLL2_PRE_PD, PLL2_PD
        2. 9.7.9.2  VCO1_DIV
        3. 9.7.9.3  OPT_REG_1
        4. 9.7.9.4  OPT_REG_2
        5. 9.7.9.5  RB_PLL1_LD_LOST, RB_PLL1_LD, CLR_PLL1_LD_LOST
        6. 9.7.9.6  RB_PLL2_LD_LOST, RB_PLL2_LD, CLR_PLL2_LD_LOST
        7. 9.7.9.7  RB_DAC_VALUE(MSB), RB_CLKinX_SEL, RB_CLKinX_LOS
        8. 9.7.9.8  RB_DAC_VALUE
        9. 9.7.9.9  RB_HOLDOVER
        10. 9.7.9.10 SPI_LOCK
  10. 10Applications and Implementation
    1. 10.1 Application Information
    2. 10.2 Digital Lock Detect Frequency Accuracy
      1. 10.2.1 Minimum Lock Time Calculation Example
    3. 10.3 Driving CLKin and OSCin Inputs
      1. 10.3.1 Driving CLKin and OSCin Pins With a Differential Source
      2. 10.3.2 Driving CLKin and OSCin Pins With a Single-Ended Source
    4. 10.4 Output Termination and Biasing
      1. 10.4.1 LVPECL
      2. 10.4.2 LVDS/HSDS
    5. 10.5 Typical Applications
      1. 10.5.1 Design Example
        1. 10.5.1.1 Design Requirements
        2. 10.5.1.2 Detailed Design Procedure
          1. 10.5.1.2.1 Device Configuration and Simulation - PLLatinum Sim
          2. 10.5.1.2.2 Device Programming
        3. 10.5.1.3 Application Curves
    6. 10.6 System Examples
      1. 10.6.1 System Level Diagram
    7. 10.7 Do's and Don'ts
  11. 11Power Supply Recommendations
    1. 11.1 Pin Connection Recommendations
      1. 11.1.1 VCC Pins and Decoupling
        1. 11.1.1.1 Clock Output Supplies
        2. 11.1.1.2 Low-Crosstalk Supplies
        3. 11.1.1.3 PLL2 Supplies
        4. 11.1.1.4 Clock Input Supplies
        5. 11.1.1.5 Unused Clock Inputs/Outputs
    2. 11.2 Current Consumption / Power Dissipation Calculations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Thermal Management
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Development Support
        1. 13.1.1.1 PLLatinum Sim
        2. 13.1.1.2 TICS Pro
    2. 13.2 Related Links
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Electrical Characteristics

(3.15 V < VCC < 3.45 V, –40 °C < TA < 85 °C and TPCB ≤ 105 °C. Typical values at VCC = 3.3 V, TA = 25 °C, at the Recommended Operating Conditions and are not assured.)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CURRENT CONSUMPTION
ICC_PD Power down supply current 1 3 mA
ICC_CLKS Supply current(2) 14 HSDS 8-mA clocks enabled
PLL1 and PLL2 locked.
565 665 mA
CLKin0/0*, CLKin1/1*, and CLKin2/2* INPUT CLOCK SPECIFICATIONS
fCLKin Clock input frequency 0.001 750 MHz
SLEWCLKin Clock input slew rate (3) 20% to 80% 0.15 0.5 V/ns
VIDCLKin Clock input
Differential input voltage (1)
Figure 8
AC coupled 0.125 1.55 |V|
VSSCLKin 0.25 3.1 Vpp
VCLKin Clock input
Single-ended input voltage
AC coupled to CLKinX;
CLKinX* AC coupled to ground
CLKinX_TYPE = 0 (bipolar)
0.25 2.4 Vpp
AC coupled to CLKinX;
CLKinX* AC coupled to ground
CLKinX_TYPE = 1 (MOS)
0.35 2.4 Vpp
|VCLKinX-offset| DC offset voltage between
CLKinX/CLKinX* (CLKinX* - CLKinX)
Each pin AC coupled, CLKin0/1/2
CLKinX_TYPE = 0 (bipolar)
0 |mV|
Each pin AC coupled, CLKin0/1
CLKinX_TYPE = 1 (MOS)
55 |mV|
DC offset voltage between
CLKin2/CLKin2* (CLKin2* - CLKin2)
Each pin AC coupled
CLKinX_TYPE = 1 (MOS)
20 |mV|
VCLKin- VIH High input voltage DC coupled to CLKinX;
CLKinX* AC coupled to ground
CLKinX_TYPE = 1 (MOS)
2.0 VCC V
VCLKin- VIL Low input voltage 0.0 0.4 V
FBCLKin/FBCLKin* and Fin/Fin* INPUT SPECIFICATIONS
fFBCLKin Clock input frequency for
zero-delay with external feedback.
AC coupled
CLKinX_TYPE = 0 (bipolar)
0.001 750 MHz
fFin Clock input frequency for
external VCO or distribution mode
AC coupled (4)
CLKinX_TYPE = 0 (bipolar)
0.001 3100 MHz
VFBCLKin/Fin Single ended
Clock input voltage
AC coupled
CLKinX_TYPE = 0 (bipolar)
0.25 2.0 Vpp
SLEWFBCLKin/Fin Slew rate on CLKin (3) AC coupled; 20% to 80%;
(CLKinX_TYPE = 0)
0.15 0.5 V/ns
PLL1 SPECIFICATIONS
fPD1 PLL1 phase detector frequency 40 MHz
ICPout1SOURCE PLL1 charge
Pump source current (5)
VCPout1 = VCC/2, PLL1_CP_GAIN = 0 50 µA
VCPout1 = VCC/2, PLL1_CP_GAIN = 1 150
VCPout1 = VCC/2, PLL1_CP_GAIN = 2 250
VCPout1 = VCC/2, PLL1_CP_GAIN = 14 1450
VCPout1 = VCC/2, PLL1_CP_GAIN = 15 1550
ICPout1SINK PLL1 charge
Pump sink current (5)
VCPout1=VCC/2, PLL1_CP_GAIN = 0 –50 µA
VCPout1=VCC/2, PLL1_CP_GAIN = 1 –150
VCPout1=VCC/2, PLL1_CP_GAIN = 2 –250
VCPout1=VCC/2, PLL1_CP_GAIN = 14 –1450
VCPout1=VCC/2, PLL1_CP_GAIN = 15 –1550
ICPout1%MIS Charge pump
Sink / source mismatch
VCPout1 = VCC/2, T = 25 °C 1% 10%
ICPout1VTUNE Magnitude of charge pump current variation vs. charge pump voltage 0.5 V < VCPout1 < VCC - 0.5 V
TA = 25 °C
4%
ICPout1%TEMP Charge pump current vs. temperature variation 4%
ICPout1 TRI Charge pump TRI-STATE leakage current 0.5 V < VCPout < VCC - 0.5 V 5 nA
PN10kHz PLL 1/f noise at 10-kHz offset. Normalized to 1-GHz output frequency PLL1_CP_GAIN = 350 µA –117 dBc/Hz
PLL1_CP_GAIN = 1550 µA –118
PN1Hz Normalized phase noise contribution PLL1_CP_GAIN = 350 µA –221.5 dBc/Hz
PLL1_CP_GAIN = 1550 µA –223
PLL2 REFERENCE INPUT (OSCin) SPECIFICATIONS
fOSCin PLL2 reference input (7) 500 MHz
SLEWOSCin PLL2 reference clock minimum slew rate on OSCin (3) 20% to 80% 0.15 0.5 V/ns
VOSCin Input voltage for OSCin or OSCin*
AC coupled; single-ended
(unused pin AC coupled to GND)
0.2 2.4 Vpp
VIDOSCin Differential voltage swing
Figure 8
AC coupled 0.2 1.55 |V|
VSSOSCin 0.4 3.1 Vpp
|VOSCin-offset| DC offset voltage between
OSCin/OSCin* (OSCinX* - OSCinX)
Each pin AC coupled 20 |mV|
fdoubler_max Doubler input frequency (6) EN_PLL2_REF_2X = 1(8);
OSCin duty cycle 40% to 60%
155 MHz
CRYSTAL OSCILLATOR MODE SPECIFICATIONS
FXTAL Crystal frequency range Fundamental mode crystal
ESR = 200 Ω (10 to 30 MHz)
ESR = 125 Ω (30 to 40 MHz)
10 40 MHz
CIN Input capacitance of OSCin port –40 to 85 °C 1 pF
PLL2 PHASE DETECTOR and CHARGE PUMP SPECIFICATIONS
fPD2 Phase detector frequency (6) 155 MHz
ICPoutSOURCE PLL2 charge pump source current (5) VCPout2=VCC/2, PLL2_CP_GAIN = 0 100 µA
VCPout2=VCC/2, PLL2_CP_GAIN = 1 400
VCPout2=VCC/2, PLL2_CP_GAIN = 2 1600
VCPout2=VCC/2, PLL2_CP_GAIN = 3 3200
ICPoutSINK PLL2 charge pump sink current (5) VCPout2=VCC/2, PLL2_CP_GAIN = 0 –100 µA
VCPout2=VCC/2, PLL2_CP_GAIN = 1 –400
VCPout2=VCC/2, PLL2_CP_GAIN = 2 –1600
VCPout2=VCC/2, PLL2_CP_GAIN = 3 –3200
ICPout2%MIS Charge pump sink/source mismatch VCPout2=VCC/2, TA = 25 °C 1% 10%
ICPout2VTUNE Magnitude of charge pump current vs. charge pump voltage variation 0.5 V < VCPout2 < VCC - 0.5 V
TA = 25 °C
4%
ICPout2%TEMP Charge pump current vs. temperature variation 4%
ICPout2TRI Charge pump leakage 0.5 V < VCPout2 < VCC - 0.5 V 10 nA
PN10kHz PLL 1/f noise at 10-kHz offset (9). Normalized to
1-GHz output frequency
PLL2_CP_GAIN = 400 µA –118 dBc/Hz
PLL2_CP_GAIN = 3200 µA –121
PN1Hz Normalized phase noise contribution (10) PLL2_CP_GAIN = 400 µA –222.5 dBc/Hz
PLL2_CP_GAIN = 3200 µA –227
INTERNAL VCO SPECIFICATIONS
fVCO LMK04821 VCO tuning range VCO0 1930 2075 MHz
VCO1(23) 2920 3080
LMK04826 VCO tuning range VCO0 1840 1970 MHz
VCO1 2440 2505
LMK04828 VCO tuning range VCO0 2370 2630 MHz
VCO1 2920 3080
KVCO LMK04821 fine tuning sensitivity LMK04821 VCO0 12 to 20 MHz/V
LMK04821 VCO1 15 to 24
LMK04826 fine tuning sensitivity LMK04826 VCO0 11 to 19 MHz/V
LMK04826 VCO1 8 to 11
LMK04828 fine tuning sensitivity LMK04828 VCO0 at 2457.6 MHz 17 to 27 MHz/V
LMK04828 VCO1 at 2949.12 MHz 17 to 23
|ΔTCL| Allowable temperature drift for continuous lock
(11)
After programming for lock, no changes to output configuration are permitted to assure continuous lock 125 °C
NOISE FLOOR
L(f)CLKout LMK04821, VCO0, noise floor
20-MHz offset(12)
245.76 MHz LVDS –158.2 dBc/Hz
HSDS 6 mA –160
HSDS 8 mA –161
HSDS 10 mA –161.4
LVPECL16 with 240 Ω –161.6
LVPECL20 with 240 Ω –162
LVPECL 161.7
L(f)CLKout LMK04821, VCO1, noise floor
20-MHz offset(12)
245.76 MHz LVDS –157.1 dBc/Hz
HSDS 6 mA –158.3
HSDS 8 mA –159
HSDS 10 mA –159.2
LVPECL16 with 240 Ω –158.8
LVPECL20 with 240 Ω –158.9
LVPECL –158.8
L(f)CLKout LMK04826, VCO0, noise floor
20-MHz offset (14)
245.76 MHz LVDS –158.1 dBc/Hz
HSDS 6 mA –159.7
HSDS 8 mA –160.8
HSDS 10 mA –161.3
LVPECL16 with 240 Ω –161.8
LVPECL20 with 240 Ω –162.0
LCPECL –161.7
L(f)CLKout LMK04826, VCO1, noise floor
20-MHz offset (14)
245.76 MHz LVDS –157.5 dBc/Hz
HSDS 6 mA –158.9
HSDS 8 mA –159.8
HSDS 10 mA –160.3
LVPECL16 with 240 Ω –160.8
LVPECL20 with 240 Ω –160.7
LCPECL –160.7
NOISE FLOOR (continued)
L(f)CLKout LMK04828, VCO0, noise floor
20-MHz offset (13)
245.76 MHz LVDS –156.3 dBc/Hz
HSDS 6 mA –158.4
HSDS 8 mA –159.3
HSDS 10 mA –158.9
LVPECL16 with 240 Ω –161.6
LVPECL20 with 240 Ω –162.5
LCPECL –162.1
L(f)CLKout LMK04828, VCO1, noise floor
20-MHz offset (13)
245.76 MHz LVDS –155.7 dBc/Hz
HSDS 6 mA –157.5
HSDS 8 mA –158.1
HSDS 10 mA –157.7
LVPECL16 with 240 Ω –160.3
LVPECL20 with 240 Ω –161.1
LCPECL –160.8
CLKout CLOSED LOOP PHASE NOISE SPECIFICATIONS a COMMERCIAL QUALITY VCXO(17)
L(f)CLKout LMK04821
VCO0
SSB phase noise (12)
245.76 MHz
Offset = 1 kHz –126.9 dBc/Hz
Offset = 10 kHz –133.5
Offset = 100 kHz –135.4
Offset = 1 MHz –149.8
Offset = 10 MHz LVDS –158.1
HSDS 8 mA –161.1
LVPECL16 with 240 Ω –161.7
L(f)CLKout LMK04821
VCO1
SSB phase noise (12)
245.76 MHz
Offset = 1 kHz –126.8 dBc/Hz
Offset = 10 kHz –133.4
Offset = 100 kHz –135.4
Offset = 1 MHz –151.8
Offset = 10 MHz LVDS –157.2
HSDS 8 mA –159.1
LVPECL16 with 240 Ω –158.9
CLKout CLOSED LOOP PHASE NOISE SPECIFICATIONS a COMMERCIAL QUALITY VCXO (continued)
L(f)CLKout LMK04826
VCO0
SSB phase noise (14)
245.76 MHz
Offset = 10 kHz –134.8 dBc/Hz
Offset = 100 kHz –135.4
Offset = 1 MHz LVDS –148.2
HSDS 8 mA
LVPECL16 with 240 Ω
–148.6
Offset = 10 MHz LVDS –157.8
HSDS 8 mA –160.4
LVPECL16 with 240 Ω –161.5
L(f)CLKout LMK04826
VCO1
SSB phase noise (14)
245.76 MHz
Offset = 10 kHz –134.3 dBc/Hz
Offset = 100 kHz –133.7
Offset = 1 MHz LVDS –152.5
HSDS 8 mA
LVPECL16 with 240 Ω
–153.6
Offset = 10 MHz LVDS –157.3
HSDS 8 mA –159.6
LVPECL16 with 240 Ω –160.5
L(f)CLKout LMK04828
VCO0
SSB phase noise (13)
245.76 MHz
Offset = 1 kHz –124.3 dBc/Hz
Offset = 10 kHz –134.7
Offset = 100 kHz –136.5
Offset = 1 MHz –148.4
Offset = 10 MHz LVDS –156.4
HSDS 8 mA –159.1
LVPECL16 with 240 Ω –160.8
L(f)CLKout LMK04828
VCO1
SSB phase noise (13)
245.76 MHz
Offset = 1 kHz –124.2 dBc/Hz
Offset = 10 kHz –134.4
Offset = 100 kHz –135.2
Offset = 1 MHz –151.5
Offset = 10 MHz LVDS –159.9
HSDS 8 mA –155.8
LVPECL16 with 240 Ω –158.1
CLKout CLOSED LOOP JITTER SPECIFICATIONS a COMMERCIAL QUALITY VCXO(17)
JCLKout LMK04821, VCO0
fCLKout = 245.76-MHz
integrated RMS jitter (12)
LVDS, BW = 12 kHz to 20 MHz 99 fs rms
HSDS 8 mA, BW = 12 kHz to 20 MHz 94
LVPECL16 with 240 Ω,
BW = 12 kHz to 20 MHz
96
LVPECL20 with 240 Ω,
BW = 12 kHz to 20 MHz
94
LCPECL with 240 Ω,
BW = 12 kHz to 20 MHz
93
LMK04821, VCO1
fCLKout = 245.76-MHz
integrated RMS jitter (12)
LVDS, BW = 12 kHz to 20 MHz 96 fs rms
HSDS 8 mA, BW = 12 kHz to 20 MHz 90
LVPECL16 with 240 Ω,
BW = 12 kHz to 20 MHz
92
LVPECL20 with 240 Ω,
BW = 12 kHz to 20 MHz
91
LCPECL with 240 Ω,
BW = 12 kHz to 20 MHz
91
CLKout CLOSED LOOP JITTER SPECIFICATIONS a COMMERCIAL QUALITY VCXO (continued)(17)
JCLKout LMK04826, VCO0
fCLKout = 245.76-MHz
integrated RMS jitter (14)
LVDS, BW = 100 Hz to 20 MHz 106 fs rms
LVDS, BW = 12 kHz to 20 MHz 104
HSDS 8 mA, BW = 100 Hz to 20 MHz 99
HSDS 8 mA, BW = 12 kHz to 20 MHz 97
LVPECL16 /w 240 Ω,
BW = 100 Hz to 20 MHz
99
LVPECL16 /w 240 Ω,
BW = 12 kHz to 20 MHz
96
LCPECL /w 240 Ω,
BW = 100 Hz to 20 MHz
100
LCPECL /w 240 Ω,
BW = 12 kHz to 20 MHz
97
LMK04826, VCO1
fCLKout = 245.76-MHz
integrated RMS jitter (14)
LVDS, BW = 100 Hz to 20 MHz 99 fs rms
LVDS, BW = 12 kHz to 20 MHz 97
HSDS 8 mA, BW = 100 Hz to 20 MHz 92
HSDS 8 mA, BW = 12 kHz to 20 MHz 90
LVPECL16 /w 240 Ω,
BW = 100 Hz to 20 MHz
91
LVPECL20 /w 240 Ω,
BW = 12 kHz to 20 MHz
89
LCPECL /w 240 Ω,
BW = 100 Hz to 20 MHz
92
LCPECL /w 240 Ω,
BW = 12 kHz to 20 MHz
89
CLKout CLOSED LOOP JITTER SPECIFICATIONS a COMMERCIAL QUALITY VCXO (continued)(17)
JCLKout LMK04828, VCO0
fCLKout = 245.76-MHz
integrated RMS jitter (13)
LVDS, BW = 100 Hz to 20 MHz 112 fs rms
LVDS, BW = 12 kHz to 20 MHz 109
HSDS 8 mA, BW = 100 Hz to 20 MHz 102
HSDS 8 mA, BW = 12 kHz to 20 MHz 99
LVPECL16 /w 240 Ω,
BW = 100 Hz to 20 MHz
98
LVPECL20 /w 240 Ω,
BW = 12 kHz to 20 MHz
95
LCPECL /w 240 Ω,
BW = 100 Hz to 20 MHz
96
LCPECL /w 240 Ω,
BW = 12 kHz to 20 MHz
93
LMK04828, VCO1
fCLKout = 245.76-MHz
integrated RMS jitter (13)
LVDS, BW = 100 Hz to 20 MHz 108 fs rms
LVDS, BW = 12 kHz to 20 MHz 105
HSDS 8 mA, BW = 100 Hz to 20 MHz 98
HSDS 8 mA, BW = 12 kHz to 20 MHz 94
LVPECL16 /w 240 Ω,
BW = 100 Hz to 20 MHz
93
LVPECL20 /w 240 Ω,
BW = 12 kHz to 20 MHz
90
LCPECL /w 240 Ω,
BW = 100 Hz to 20 MHz
91
LCPECL /w 240 Ω,
BW = 12 kHz to 20 MHz
88
DEFAULT POWER on RESET CLOCK OUTPUT FREQUENCY
fCLKout-startup Default output clock frequency at device power on (18)(19) LMK04826 235 MHz
LMK04828 315
fOSCout OSCout frequency (6) 500 MHz
CLOCK SKEW and DELAY
|TSKEW| DCLKoutX to SDCLKoutY
FCLK = 245.76 MHz, RL= 100 Ω
AC coupled (15)
Same pair, same format (16)
SDCLKoutY_MUX = 0 (device clock)
25 |ps|
Maximum DCLKoutX or SDCLKoutY
to DCLKoutX or SDCLKoutY
FCLK = 245.76 MHz, RL= 100 Ω
AC coupled
Any pair, same format (16)
SDCLKoutY_MUX = 0 (device clock)
50
tsJESD204B SYSREF to device clock setup time base reference.
See SYSREF to Device Clock Alignment to adjust SYSREF to device clock setup time as required.
SDCLKoutY_MUX = 1 (SYSREF)
SYSREF_DIV = 30
SYSREF_DDLY = 8 (global)
SDCLKoutY_DDLY = 1 (2 cycles, local)
DCLKoutX_MUX = 1 (Div+DCC+HS)
DCLKoutX_DIV = 30
DCLKoutX_DDLY_CNTH = 7
DCLKoutX_DDLY_CNTL = 6
DCLKoutX_HS = 0
SDCLKoutY_HS = 0
–80 ps
tPDCLKin0_
SDCLKout1
Propagation delay from CLKin0 to SDCLKout1 CLKin0_OUT_MUX = 0 (SYSREF mux)
SYSREF_CLKin0_MUX = 1 (CLKin0)
SDCLKout1_PD = 0
SDCLKout1_DDLY = 0 (bypass)
SDCLKout1_MUX = 1 (SR)
EN_SYNC = 1
LVPECL16 /w 240 Ω
0.65 ns
fADLYmax Maximum analog delay frequency DCLKoutX_MUX = 4 1536 MHz
LVDS CLOCK OUTPUTS (DCLKoutX, SDCLKoutY, and OSCout)
VOD Differential output voltage T = 25 °C, DC measurement
AC coupled to receiver input
RL = 100-Ω differential termination
395 |mV|
ΔVOD Change in magnitude of VOD for complementary output states –60 60 mV
VOS Output offset voltage 1.125 1.25 1.375 V
ΔVOS Change in VOS for complementary output states 35 |mV|
TR / TF Output rise time 20% to 80%, RL = 100 Ω, 245.76 MHz 180 ps
Output fall time 80% to 20%, RL = 100 Ω
ISA
ISB
Output short circuit current - single ended Single-ended output shorted to GND
T = 25 °C
–24 24 mA
ISAB Output short circuit current - differential Complimentary outputs tied together –12 12 mA
6-mA HSDS CLOCK OUTPUTS (DCLKoutX and SDCLKoutY)
VOH T = 25 °C, DC measurement
Termination = 50 Ω to
VCC - 1.42 V
VCC - 1.05
VOL VCC - 1.64
VOD Differential output voltage 590 |mV|
ΔVOD Change in VOD for complementary output states –80 80 mVpp
8-mA HSDS CLOCK OUTPUTS (DCLKoutX and SDCLKoutY)
TR / T F Output rise time 245.76 MHz, 20% to 80%, RL = 100 Ω 170 ps
Output fall time 245.76 MHz, 80% to 20%, RL = 100 Ω
VOH T = 25 °C, DC measurement
Termination = 50 Ω to
VCC - 1.64 V
VCC - 1.26
VOL VCC –2.06
VOD Differential output voltage 800 |mV|
ΔVOD Change in VOD for complementary output states –115 115 mVpp
10-mA HSDS CLOCK OUTPUTS (DCLKoutX and SDCLKoutY)
VOH T = 25 °C, DC measurement
Termination = 50 Ω to
VCC - 1.43 V
VCC - 0.99
VOL VCC - 1.97
VOD 980 |mv|
ΔVOD Change in VOD for complementary output states –115 115 mVpp
LVPECL CLOCK OUTPUTS (DCLKoutX and SDCLKoutY)
TR / TF 20% to 80% output rise RL = 100 Ω, emitter resistors = 240 Ω to GND
DCLKoutX_TYPE = 4 or 5
(1600 or 2000 mVpp)
150 ps
80% to 20% output fall time
1600-mVpp LVPECL CLOCK OUTPUTS (DCLKoutX and SDCLKoutY)
VOH Output high voltage DC measurement
Termination = 50 Ω to
VCC - 2.0 V
VCC - 1.04 V
VOL Output low voltage VCC - 1.80 V
VOD Output voltage
Figure 9
760 |mV|
2000-mVpp LVPECL CLOCK OUTPUTS (DCLKoutX and SDCLKoutY)
VOH Output high voltage DC measurement
Termination = 50 Ω to VCC - 2.3 V
VCC - 1.09 V
VOL Output low voltage VCC - 2.05 V
VOD Output voltage
Figure 9
960 |mV|
LCPECL CLOCK OUTPUTS (DCLKoutX and SDCLKoutY)
VOH Output high voltage DC measurement
Termination = 50 Ω to 0.5 V
1.57 V
VOL Output low voltage 0.62 V
VOD Output voltage
Figure 9
950 |mV|
LVCMOS CLOCK OUTPUTS (OSCout)
fCLKout Maximum frequency
(20)
5-pF load 250 MHz
VOH Output high voltage 1-mA load VCC - 0.1 V
VOL Output low voltage 1-mA load 0.1 V
IOH Output high current (source) VCC = 3.3 V, VO = 1.65 V 28 mA
IOL Output low current (sink) VCC = 3.3 V, VO = 1.65 V 28 mA
DUTYCLK Output duty cycle(22) VCC/2 to VCC/2,
FCLK = 100 MHz, T = 25 °C
50%
TR Output rise time 20% to 80%, RL = 50 Ω, CL = 5 pF 400 ps
TF Output fall time 80% to 20%, RL = 50 Ω, CL = 5 pF 400 ps
DIGITAL OUTPUTS (CLKin_SELX, Status_LDX, and RESET/GPO)
VOH High-level output voltage IOH = –500 µA
CLKin_SELX_TYPE = 3 or 4
Status_LDX_TYPE = 3 or 4
RESET_TYPE = 3 or 4
VCC - 0.4 V
VOL Low-level output voltage IOL = 500 µA
CLKin_SELX_TYPE = 3, 4, or 6
Status_LDX_TYPE = 3, 4, or 6
RESET_TYPE = 3, 4, or 6
0.4 V
DIGITAL OUTPUT (SDIO)
VOH High-level output voltage IOH = –500 µA ; During SPI read.
SDIO_RDBK_TYPE = 0
VCC - 0.4 V
VOL Low-level output voltage IOL = 500 µA ; During SPI read.
SDIO_RDBK_TYPE = 0 or 1
0.4 V
DIGITAL INPUTS (CLKinX_SEL, RESET/GPO, SYNC, SCK, SDIO, or CS*)
VIH High-level input voltage 1.2 VCC V
VIL Low-level input voltage 0.4 V
DIGITAL INPUTS (CLKinX_SEL)
IIH High-level input current
VIH = VCC
CLKin_SELX_TYPE = 0,
(high impedance)
–5 5 µA
CLKin_SELX_TYPE = 1 (pull-up) –5 5
CLKin_SELX_TYPE = 2 (pull-down) 10 80
IIL Low-level input current
VIL = 0 V
CLKin_SELX_TYPE = 0,
(high impedance)
–5 5 µA
CLKin_SELX_TYPE = 1 (pull-up) –40 –5
CLKin_SELX_TYPE = 2 (pull-down) –5 5
DIGITAL INPUT (RESET/GPO)
IIH High-level input current
VIH = VCC
RESET_TYPE = 2
(pull-down)
10 80 µA
IIL Low-level input current
VIL = 0 V
RESET_TYPE = 0 (high impedance) –5 5 µA
RESET_TYPE = 1 (pull-up) –40 –5
RESET_TYPE = 2 (pull-down) –5 5
DIGITAL INPUTS (SYNC)
IIH High-level input current VIH = VCC 25 µA
IIL Low-level input current VIL = 0 V –5 5
DIGITAL INPUTS (SCK, SDIO, CS*)
IIH High-level input current VIH = VCC –5 5 µA
IIL Low-level input current VIL = 0 –5 5 µA
DIGITAL INPUT TIMING
tHIGH RESET pin held high for device reset 25 ns
See Differential Voltage Measurement Terminology for definition of VID and VOD voltages.
See the applications section of Power Supply Recommendations for Icc for specific part configuration and how to calculate Icc for a specific design.
To meet the jitter performance listed in the subsequent sections of this data sheet, the minimum recommended slew rate for all input clocks is 0.5 V/ns. This is especially true for single-ended clocks. Phase-noise performance begins to degrade as the clock input slew rate is reduced. However, the device will function at slew rates down to the minimum listed. When compared to single-ended clocks, differential clocks (LVDS, LVPECL) are less susceptible to degradation in phase-noise performance at lower slew rates, due to their common-mode noise rejection. However, TI also recommends using the highest possible slew rate for differential clocks to achieve optimal phase-noise performance at the device outputs.
Assured by characterization. ATE tested at 2949.12 MHz.
This parameter is programmable.
Assured by characterization. ATE tested at 122.88 MHz.
FOSCin maximum frequency assured by characterization. Production tested at 122.88 MHz.
The EN_PLL2_REF_2X bit enables or disables a frequency doubler mode for the PLL2 OSCin path.
A specification in modeling PLL in-band phase noise is the 1/f flicker noise, LPLL_flicker(f), which is dominant close to the carrier. Flicker noise has a 10-dB/decade slope. PN10kHz is normalized to a 10-kHz offset and a 1-GHz carrier frequency. PN10kHz = LPLL_flicker(10 kHz) - 20log(Fout / 1 GHz), where LPLL_flicker(f) is the single side band phase noise of only the flicker noise's contribution to total noise, L(f). To measure LPLL_flicker(f), it is important to be on the 10-dB/decade slope close to the carrier. A high compare frequency and a clean crystal are important to isolating this noise source from the total phase noise, L(f). LPLL_flicker(f) can be masked by the reference oscillator performance if a low power or noisy source is used. The total PLL in-band phase noise performance is the sum of LPLL_flicker(f) and LPLL_flat(f).
A specification modeling PLL in-band phase noise. The normalized phase noise contribution of the PLL, LPLL_flat(f), is defined as: PN1HZ=LPLL_flat(f) - 20log(N) - 10log(fPDX). LPLL_flat(f) is the single side band phase noise measured at an offset frequency, f, in a 1-Hz bandwidth and fPDX is the phase-detector frequency of the synthesizer. LPLL_flat(f) contributes to the total noise, L(f).
Maximum allowable temperature drift for continuous lock is how far the temperature can drift in either direction from the value it was at the time that the 0x168 register was last programmed with PLL2_FCAL_DIS = 0, and still have the part stay in lock. The action of programming the 0x168 register, even to the same value, activates a frequency calibration routine. This implies the part will work over the entire frequency range, but if the temperature drifts more than the maximum allowable drift for continuous lock, then it is necessary to reload the appropriate register to ensure it stays in lock. Regardless of what temperature the part was initially programmed at, the temperature can never drift outside the frequency range of –40 °C to 85 °C without violating specifications.
Data collected using a Prodyn BIB-100G balun. Loop filter is C1 = 47 pF, C2 = 3.9 nF, R2 = 620 Ω, C3 = 10 pF, R3 = 200 Ω, C4 = 10 pF, R4 = 200 Ω, PLL1_CP = 450 µA, PLL2_CP = 3.2 mA.. VCO0 PLL2 loop filter bandwidth = 288 kHz, phase margin = 72 degrees. VCO1 Loop filter loop bandwidth = 221 kHz, phase margin = 70 degrees. CLKoutX_Y_IDL = 1, CLKoutX_Y_ODL = 0.
Data collected using ADT2-1T+ balun. Loop filter is C1 = 47 pF, C2 = 3.9 nF, R2 = 620 Ω, C3 = 10 pF, R3 = 200 Ω, C4 = 10 pF, R4 = 200 Ω, PLL1_CP = 450 µA, PLL2_CP = 3.2 mA.. VCO0 loop filter bandwidth = 344 kHz, phase margin = 73 degrees. VCO1 Loop filter loop bandwidth = 233 kHz, phase margin = 70 degrees. CLKoutX_Y_IDL = 1, CLKoutX_Y_ODL = 0.
Data collected using a Prodyn BIB-100G balun. Loop filter for PLL2 is C1 = 47 pF, C2 = 3.9 nF, R2 = 620 Ω, C3 = 10 pF, R3 = 200 Ω, C4 = 10 pF, R4 = 200 Ω, PLL1_CP = 450 µA, PLL2_CP = 3.2 mA.. VCO0 loop filter bandwidth = 303 kHz, phase margin = 73 degrees. VCO1 Loop filter loop bandwidth = 151 kHz, phase margin = 64 degrees. CLKoutX_Y_IDL = 1, CLKoutX_Y_ODL = 0.
Equal loading and identical clock output configuration on each clock output is required for specification to be valid. Specification not valid for delay mode.
LVPECL uses a 120-Ω emitter resistor, LVDS and HSDS uses a 560-Ω shunt.
VCXO used is a 122.88-MHz Crystek CVHD-950-122.880.
OSCout oscillates at start-up at the frequency of the VCXO attached to the OSCin port.
LMK04821 has no DCLKoutX or SDCLKoutY outputs which oscillate at power on. Only OSCout oscillates at power on.
Assured by characterization. ATE tested to 10 MHz.
20 MHz
Assumes OSCin has 50% input duty cycle.
The VCO1 divider, VCO1_DIV in register 0x174, can be programmed to ÷2 to ÷8 resulting in a lower effective VCO frequency range, as shown in Device Configuration Information.