JAJSJM9A December   2020  – January 2022 LMK1C1106 , LMK1C1108

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Fail-Safe Inputs
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

VDD = 3.3 V ± 5 %, –40°C ≤ TA ≤ 125°C. Typical values are at VDD = 3.3 V, 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CURRENT CONSUMPTION
IDD Core supply current, static All-outputs disabled, fIN = 0 V 25 45 µA
IDD Core supply current All-outputs disabled, fIN = 100 MHz, VDD = 1.8 V 2 6 mA
IDD Core supply current All-outputs disabled, fIN = 100 MHz, VDD = 2.5 V 6.5 10 mA
IDD Core supply current All-outputs disabled, fIN = 100 MHz, VDD = 3.3 V 15 21 mA
IDD Output current Per output, fIN = 100 MHz, CL = 5pF, VDD = 1.8 V 3.2 3.5
Per output, fIN = 100 MHz, CL = 5pF, VDD = 2.5 V 4.6 5.5
Per output, fIN = 100 MHz, CL = 5pF, VDD = 3.3 V 6 7
CLOCK INPUT
fIN_SE Input frequency VDD = 3.3 V DC 250 MHz
VDD = 2.5 V and 1.8 V DC 200
VIH Input high voltage 0.7 x VDD V
VIL Input low voltage 0.3 x VDD
dVIN/dt Input slew rate 20% - 80% of input swing 0.1 V/ns
IIN_LEAK Input leakage current –50 50 uA
CIN_SE Input capacitance at 25°C 7 pF
CLOCK OUTPUT FOR ALL VDD LEVELS
fOUT Output frequency VDD = 3.3 V 250 MHz
VDD = 2.5 V and 1.8 V 200
ODC Output duty cycle With 50% duty cycle input 45 55 %
t1G_ON Output enable time See (1) 5 cycles
t1G_OFF Output disable time See (2) 5 cycles
CLOCK OUTPUT FOR VDD = 3.3 V ± 5%
VOH Output high voltage IOH = 1 mA 2.8 V
VOL Output low voltage IOL = 1 mA 0.2
tRISE-FALL Output rise and fall time 20/80%, CL= 5 pF, fIN = 156.25 MHz 0.3 0.7 ns
tOUTPUT-SKEW Output-output skew See (3) 35 55 ps
tPART-SKEW Part-to-part skew 280
tPROP-DELAY Propagation delay See (4) 1.3 2.2 ns
tJITTER-ADD Additive Jitter fIN = 156.25 MHz, Input slew rate = 1.6 V/ns, Integration range = 12 kHz - 20 MHz 12 20 fs, RMS
ROUT Output impedance 50 Ω
CLOCK OUTPUT FOR VDD = 2.5 V ± 5%
VOH Output high voltage IOH = 1 mA 0.8 x VDD V
VOL Output low voltage IOL = 1 mA 0.2 x VDD
tRISE-FALL Output rise and fall time 20/80%, CL= 5 pF, fIN = 156.25 MHz 0.33 0.8 ns
tOUTPUT-SKEW Output-output skew See (3) 55 ps
tPART-SKEW Part-to-part skew 450
tPROP-DELAY Propagation delay See (4) 1.5 2.5 ns
tJITTER-ADD Additive Jitter fIN = 156.25 MHz, Input slew rate = 1.2 V/ns, Integration range = 12 kHz - 20 MHz 15 27 fs, RMS
ROUT Output impedance 55 Ω
CLOCK OUTPUT FOR VDD = 1.8 V ± 5%
VOH Output high voltage IOH = 1 mA 0.8 x VDD V
VOL Output low voltage IOL = 1 mA 0.2 x VDD
tRISE-FALL Output rise and fall time 20/80%, CL= 5 pF, fIN = 156.25 MHz 0.38 1 ns
tOUTPUT-SKEW Output-output skew See (3) 55 ps
tPART-SKEW Part-to-part skew 930 ps
tPROP-DELAY Propagation delay See (4) 1.5 3 ns
tJITTER-ADD Additive Jitter fIN = 156.25 MHz, Input slew rate = 1.2 V/ns, Integration range = 12 kHz - 20 MHz 28 60 fs, RMS
ROUT Output impedance 64 Ω
GENERAL PURPOSE INPUT (1G)
VIH High-level input voltage 0.75 x VDD V
VIL Low-level input voltage 0.25 x VDD
IIH Input high-level current VIH = VDD_REF –50 50 µA
IIL Input low-level current VIL = GND –50 50
(1) Measured from 1G rising edge crossing VIH to first rising edge of Yn.
(2) Measured from 1G falling edge crossing VIL to last falling edge of Yn.
(3) Measured from rising edge of any Yn output to any other Ym output.
(4) Measured from rising edge of CLKIN to any Yn output.