SNAS634B March   2014  – January 2016 LMP92066

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Simplified Schematic
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Output Switching Characteristics
    8. 7.8 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Features Description
      1. 8.3.1 Temperature Sensor
      2. 8.3.2 Look-Up-Table (LUT) and Arithmetic-Logic Unit (ALU)
        1. 8.3.2.1 LUT and ALU Organization
        2. 8.3.2.2 LUT Coefficient to Register Mapping
        3. 8.3.2.3 The LUT Input and Output Ranges
      3. 8.3.3 Analog Signal Path
        1. 8.3.3.1 DAC
        2. 8.3.3.2 Buffer Amplifier
        3. 8.3.3.3 Output On and Off Control
      4. 8.3.4 Memory
        1. 8.3.4.1 READ and WRITE Access
        2. 8.3.4.2 Access Control
        3. 8.3.4.3 LUT, NOTEPAD Storage, and EEPROM
      5. 8.3.5 I2C Interface
        1. 8.3.5.1 Supported Data Transfer Formats
        2. 8.3.5.2 Slave Address Selection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Default Operating Mode
      2. 8.4.2 Temperature Sensor Override
      3. 8.4.3 ALU Bypass
      4. 8.4.4 DAC Input Override
      5. 8.4.5 LDMOS and GaN Drives
    5. 8.5 Programming
      1. 8.5.1  Temperature Sensor Output Data Access Registers
      2. 8.5.2  DAC Input Data Registers
      3. 8.5.3  Temperature Sensor Status Register
      4. 8.5.4  Override Control Register
      5. 8.5.5  Override Data Registers
      6. 8.5.6  EEPROM Control Register
      7. 8.5.7  Software RESET Register
      8. 8.5.8  Access Control Register
      9. 8.5.9  Block I2C Access Control Register
      10. 8.5.10 I2C Address LOCK Register
      11. 8.5.11 Output Drive Supply Status Register
      12. 8.5.12 Device Version Register
      13. 8.5.13 EEPROM Burn Counter
      14. 8.5.14 LUT Coefficient Registers
      15. 8.5.15 LUT Control Registers
      16. 8.5.16 Notepad Registers
    6. 8.6 Register Map
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Temperature Compensated Bias Generator for LDMOS Power Amplifer (PA)
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Requirements
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Temperature Compensated Bias Generator for GaN Power Amplifer (PA)
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
    3. 9.3 Do's and Don'ts
      1. 9.3.1 Output Drive Switching
    4. 9.4 Initialization Setup
      1. 9.4.1 Factory Default
      2. 9.4.2 At Power Up
  10. 10Power Supply Recommendations
    1. 10.1 VDD Supply Sourcing
    2. 10.2 IVDD During EEPROM BURN
    3. 10.3 IVDD During EEPROM TRANSFER
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

10 Power Supply Recommendations

The device rails VIO, VDD, and VDDB (VSSB in GaN mode) should be supplied from a well-regulated power supply capable of sourcing at least 50 mA. The required supply levels are shown in the Specifications tables of this document. Along with ceramic bypass capacitors, additional bulk capacitance is recommended on the VDD node. The function of this bulk capacitance is to provide the momentary increases in the supply current requirements due to the EEPROM activity. An electrolytic capacitor with a value of 10 μF to 47 μF is a typical choice.

10.1 VDD Supply Sourcing

The power supply powering the VDD pin must be capable of sourcing a minimum of 50mA. This is required in order to avoid the continuous activation of the LMP92066’s power-on-reset (POR) circuit. When the VDD supply rail passes through the POR voltage of approximately 4.2V (either rising or falling edge), an increase in supply current occurs. If the power supply is not capable of sourcing the 50mA that is required under worst case conditions, the voltage supplied to VDD will not increase beyond the POR voltage level and the LMP92066’s POR circuitry remains active and continues to draw excess current. This excess current draw is approximately 20mA under nominal conditions.

Since the LMP92066’s POR circuitry also responds to the discharge (falling edge) of the supply line, an increase in supply current occurs when the VDD supply is turned off as well. Similar to the condition described above, if the VDD supply is not capable of sourcing a minimum of 50mA, an increase in VDD supply current can be experienced if the VDD supply is immediately ramped back up after being discharged. Under this circumstance, the increase in VDD supply current will persist until the voltage surpasses 4.2V. This is a result of the POR circuitry never turning off. The POR circuit will only turn off once the VDD supply has passed through the POR voltage level of 4.2V.

10.2 IVDD During EEPROM BURN

Figure 51 shows the transient behavior of IVDD due to the EEPROM BURN operation. VSDA trace activity is used as the trigger. The triggering event is the BURN command sent via the I2C interface. During the BURN the IVDD increases to almost 4 mA for 125 ms. The 10-mA peaking in IVDD is due to the TRANSFER of newly stored data from EEPROM back to the operating memory – this is part of the internal error detection and correction process.

LMP92066 C021_snas634.gif
IVDD = 2mA/div VSDA = 5V/div
Figure 51. IVDD Transient During EEPROM BURN

10.3 IVDD During EEPROM TRANSFER

The transfer of data, from the EEPROM to the operating memory, results in the temporary increase in supply current IVDD. The total IVDD increases to about 10 mA for the duration of the TRANFER operation, typically 200 µs. Given the infrequent occurrence, and the short duration, the increased IVDD can be easily supplied by the external bulk capacitors; that is, this does not represent an additional burden to the system power supply. The typical IVDD transient during TRANSFER is shown in Figure 52. The triggering event is the TRANSFER command issued via the I2C interface.

LMP92066 C022_snas634.gif
IVDD = 2mA/div VSDA = 5V/div
Figure 52. IVDD Transient During EEPROM Transfer

The TRANSFER operation occurs due to the following:

  1. Power-On RESET
  2. Software RESET
  3. EEPROM TRANSFER command issued via the I2C interface
  4. Upon completion of the EEPROM BURN operation, as a data verification step.