SNOSC69D April   2012  – March 2017 LMV611 , LMV612 , LMV614

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - 1.8 V (DC)
    6. 6.6  Electrical Characteristics - 1.8 V (AC)
    7. 6.7  Electrical Characteristics - 2.7 V (DC)
    8. 6.8  Electrical Characteristics - 2.7 V (AC)
    9. 6.9  Electrical Characteristics - 5 V (DC)
    10. 6.10 Electrical Characteristics - 5 V (AC)
    11. 6.11 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input and Output Stage
    4. 7.4 Device Functional Modes
      1. 7.4.1 Input Bias Current Consideration
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Half-Wave Rectifier With Rail-to-Ground Output Swing
      2. 8.1.2 Instrumentation Amplifier With Rail-to-Rail Input and Output
    2. 8.2 Typical Applications
      1. 8.2.1 High-Side Current Sensing
        1. 8.2.1.1 Design Requirements
          1. 8.2.1.1.1 Custom Design With WEBENCH® Tools
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Custom Design With WEBENCH® Tools
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 Community Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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7 Detailed Description

7.1 Overview

The LMV61x devices achieve a gain bandwidth of 1.4 MHz while drawing 100-µA (typical) quiescent current. They also provide a rail-to-rail input with a maximum input offset voltage of 4 mV. Lastly, the LMV61x input common mode extends 200 mV beyond the supplies and the output can swing rail-to-rail unloaded and within
30 mV with 2-kΩ load at 1.8-V supply.

7.2 Functional Block Diagram

LMV611 LMV612 LMV614 30185601.gif

7.3 Feature Description

7.3.1 Input and Output Stage

The rail-to-rail input stage of this family provides more flexibility for the designer. The LMV61x use a complimentary PNP and NPN input stage in which the PNP stage senses common-mode voltage near V− and the NPN stage senses common-mode voltage near V+. The transition from the PNP stage to NPN stage occurs
1 V below V+. Because both input stages have their own offset voltage, the offset of the amplifier becomes a function of the input common-mode voltage and has a crossover point at 1 V below V+.

This VOS crossover point can create problems for both DC- and AC-coupled signals if proper care is not taken. Large input signals that include the VOS crossover point causes distortion in the output signal. One way to avoid such distortion is to keep the signal away from the crossover. For example, in a unity-gain buffer configuration and with VS = 5 V, a 5-V peak-to-peak signal contains input-crossover distortion while a 3-V peak-to-peak signal centered at 1.5 V does not contain input-crossover distortion as it avoids the crossover point. Another way to avoid large signal distortion is to use a gain of −1 circuit which avoids any voltage excursions at the input terminals of the amplifier. In that circuit, the common-mode DC voltage can be set at a level away from the VOS crossover point. For small signals, this transition in VOS shows up as a VCM dependent spurious signal in series with the input signal and can effectively degrade small signal parameters such as gain and common-mode rejection ratio. To resolve this problem, the small signal must be placed such that it avoids the VOS crossover point. In addition to the rail-to-rail performance, the output stage can provide enough output current to
drive 600-Ω loads. Because of the high current capability, take care to not exceed the 150°C maximum junction temperature specification.

7.4 Device Functional Modes

7.4.1 Input Bias Current Consideration

The LMV61x family has a complementary bipolar input stage. The typical input bias current (IB) is 15 nA. The input bias current can develop a significant offset voltage. This offset is primarily due to IB flowing through the negative feedback resistor, RF. For example, if IB is 50 nA and RF is 100 kΩ, then an offset voltage of 5 mV develops (VOS = IB × RF). Using a compensation resistor (RC), as shown in Figure 29, cancels this effect. But the input offset current (IOS) still contributes to an offset voltage in the same manner.

LMV611 LMV612 LMV614 30185659.gif Figure 29. Canceling Offset Voltage Due to Input Bias Current