SNAS404B May 2007 – January 2016 LMX2487E
PRODUCTION DATA.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
This device ideal for use in a broad class of applications, especially those requiring low current consumption and low fractional spurs. For applications that only need a single PLL, the unused PLL can be powered down and will not draw any extra current or generate any spurs or crosstalk.
Table 47 lists the design parameters of the LMX2487E.
PARAMETER | VALUE | |
---|---|---|
PM | Phase Margin | 48.6 degrees |
BW | Loop Bandwidth | 9.3 KHz |
T3/T1 | Pole Ratio | 39.70% |
T4/T3 | 39.20% | |
KPD | Charge Pump Gain | 8X (760 µA) |
fPD | Phase Detector Frequency | 20 MHz |
fVCO | VCO Frequency | 6000-6030 |
Vcc | Supply Votlage | 3 V |
KVCO | VCO Gain | 20 MHz/V |
CVCO | VCO Input Capacitance | 50 pF |
C1_LF | Loop Filter Component | 2.2 nF |
C2_LF | 39 nF | |
C3_LF | 220 pF | |
C4_LF | 100 pF | |
R2_LF | 1.2 kΩ | |
R3_LF | 4.7 kΩ | |
R4_LF | 10 kΩ |
The design of the loop filter involves balancing requirements of lock time, spurs, and phase noise. This design is fairly involved, but the TI website has references, design tools, and simulation tools cover the loop filter design and simulation in depth.