JAJSCK2A October   2016  – January 2017 LMX2491

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Storage Conditions
    3. 6.3 ESD Ratings
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Timing Requirements, Programming Interface (CLK, DATA, LE)
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  OSCin Input
      2. 7.3.2  OSCin Doubler
      3. 7.3.3  R Divider
      4. 7.3.4  PLL N Divider
      5. 7.3.5  Fractional Circuitry
      6. 7.3.6  PLL Phase Detector and Charge Pump
      7. 7.3.7  External Loop Filter
      8. 7.3.8  Fastlock and Cycle Slip Reduction
      9. 7.3.9  Lock Detect and Charge Pump Voltage Monitor
        1. 7.3.9.1 Charge Pump Voltage Monitor
        2. 7.3.9.2 Digital Lock Detect
      10. 7.3.10 FSK/PSK Modulation
      11. 7.3.11 Ramping Functions
        1. 7.3.11.1 Ramp Count
        2. 7.3.11.2 Ramp Comparators and Ramp Limits
      12. 7.3.12 Power-on-reset (POR)
      13. 7.3.13 Register Readback
    4. 7.4 Device Functional Modes
      1. 7.4.1 Continuous Frequency Generator
        1. 7.4.1.1 Integer Mode Operation
        2. 7.4.1.2 Fractional Mode Operation
      2. 7.4.2 Modulated Waveform Generator
    5. 7.5 Programming
      1. 7.5.1 Loading Registers
    6. 7.6 Register Maps
      1. 7.6.1 Register Field Descriptions
        1. 7.6.1.1 POWERDOWN and Reset Fields
        2. 7.6.1.2 Dividers and Fractional Controls
          1. 7.6.1.2.1 Speed Up Controls (Cycle Slip Reduction and Fastlock)
      2. 7.6.2 Lock Detect and Charge Pump Monitoring
      3. 7.6.3 TRIG1, TRIG2, MOD, and MUXout Pins
      4. 7.6.4 Ramping Functions
      5. 7.6.5 Individual Ramp Controls
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1  Design Requirements
      2. 8.2.2  Detailed Design Procedure
      3. 8.2.3  TICS Pro Basic Setup
      4. 8.2.4  Frequency Shift Keying Example
      5. 8.2.5  Single Sawtooth Ramp Example
      6. 8.2.6  Continuous Sawtooth Ramp Example
      7. 8.2.7  Continuous Sawtooth Ramp with FSK Example
      8. 8.2.8  Continuous Triangular Ramp Example
      9. 8.2.9  Continuous Trapezoid Ramp Example
      10. 8.2.10 Arbitrary Waveform Ramp Example
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 開発サポート
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

RTW Package
24-Pin VQFN
Top View
LMX2491 po_snas624.gif

Pin Functions

TERMINAL TYPE DESCRIPTION
NO. NAME
0 DAP GND Die Attach Pad. Connect to PCB ground plane.
1 GND GND Ground for charge pump.
2, 3 GND GND Ground for Fin Buffer
4, 5 Fin
Fin*		 Input Complimentary high frequency input pins. Should be AC-coupled. If driving single-ended, impedance as seen from Fin and Fin* pins looking outwards from the part should be roughly the same.
6 Vcc Supply Power Supply for Fin Buffer
7 Vcc Supply Supply for On-chip LDOs
8 Vcc Supply Supply for OSCin Buffer
9 OSCin Input Reference Frequency Input
10 GND/
OSCin*		 GND/Input Complimentary input for OSCin.
If not used, it is recommended to match the termination as seen from the OSCin terminal looking outwards. However, this may also be grounded as well.
11 GND GND Ground for OSCin Buffer
12 MOD Input/Output Multiplexed Input/Output Pins for Ramp Triggers, FSK/PSK Modulation, FastLock, and Diagnostics
13 CE Input Chip Enable
14 CLK GND Serial Programming Clock.
15 DATA GND Serial Programming Data
16 LE Input Serial Programming Latch Enable
17 MUXout Input/Output Multiplexed Input/Output Pins for Ramp Triggers, FSK/PSK Modulation, FastLock, and Diagnostics
18 Vcc Supply Supply for delta sigma engine.
19 Vcc Supply Supply for general circuitry.
20 TRIG1 Input/Output Multiplexed Input/Output Pins for Ramp Triggers, FSK/PSK Modulation, FastLock, and Diagnostics
21 TRIG2 Input/Output Multiplexed Input/Output Pins for Ramp Triggers, FSK/PSK Modulation, FastLock, and Diagnostics
22 Vcp Supply Power Supply for the charge pump.
23 Rset NC No connect.
24 CPout Output Charge Pump Output