JAJSCK2A October   2016  – January 2017 LMX2491

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Storage Conditions
    3. 6.3 ESD Ratings
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Timing Requirements, Programming Interface (CLK, DATA, LE)
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  OSCin Input
      2. 7.3.2  OSCin Doubler
      3. 7.3.3  R Divider
      4. 7.3.4  PLL N Divider
      5. 7.3.5  Fractional Circuitry
      6. 7.3.6  PLL Phase Detector and Charge Pump
      7. 7.3.7  External Loop Filter
      8. 7.3.8  Fastlock and Cycle Slip Reduction
      9. 7.3.9  Lock Detect and Charge Pump Voltage Monitor
        1. 7.3.9.1 Charge Pump Voltage Monitor
        2. 7.3.9.2 Digital Lock Detect
      10. 7.3.10 FSK/PSK Modulation
      11. 7.3.11 Ramping Functions
        1. 7.3.11.1 Ramp Count
        2. 7.3.11.2 Ramp Comparators and Ramp Limits
      12. 7.3.12 Power-on-reset (POR)
      13. 7.3.13 Register Readback
    4. 7.4 Device Functional Modes
      1. 7.4.1 Continuous Frequency Generator
        1. 7.4.1.1 Integer Mode Operation
        2. 7.4.1.2 Fractional Mode Operation
      2. 7.4.2 Modulated Waveform Generator
    5. 7.5 Programming
      1. 7.5.1 Loading Registers
    6. 7.6 Register Maps
      1. 7.6.1 Register Field Descriptions
        1. 7.6.1.1 POWERDOWN and Reset Fields
        2. 7.6.1.2 Dividers and Fractional Controls
          1. 7.6.1.2.1 Speed Up Controls (Cycle Slip Reduction and Fastlock)
      2. 7.6.2 Lock Detect and Charge Pump Monitoring
      3. 7.6.3 TRIG1, TRIG2, MOD, and MUXout Pins
      4. 7.6.4 Ramping Functions
      5. 7.6.5 Individual Ramp Controls
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1  Design Requirements
      2. 8.2.2  Detailed Design Procedure
      3. 8.2.3  TICS Pro Basic Setup
      4. 8.2.4  Frequency Shift Keying Example
      5. 8.2.5  Single Sawtooth Ramp Example
      6. 8.2.6  Continuous Sawtooth Ramp Example
      7. 8.2.7  Continuous Sawtooth Ramp with FSK Example
      8. 8.2.8  Continuous Triangular Ramp Example
      9. 8.2.9  Continuous Trapezoid Ramp Example
      10. 8.2.10 Arbitrary Waveform Ramp Example
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 開発サポート
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VCP Supply voltage for charge pump VCC 5.5 V
VCC Supply voltage –0.3 3.6 V
VIN I/O input voltage –0.3 VCC + 0.3 V
TSolder Lead temperature (solder 4 seconds) 260 °C
TJunction Junction temperature 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 Storage Conditions

applicable before the DMD is installed in the final product
MIN MAX UNIT
Tstg DMD storage temperature –65 150 °C
TDP Storage dew point 3 °C

6.3 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2500 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
PARAMETER MIN NOM MAX UNIT
VCC Supply voltage 3.15 3.3 3.45 V
VCP Charge pump supply voltage VCC 5.25 V
TA Ambient temperature –40 85 °C
TJ Junction temperature –40 125 °C

6.5 Thermal Information

THERMAL METRIC(1) LMX2491 UNIT
RTW (VQFN)
24 PINS
RθJA Junction-to-ambient thermal resistance 39.4 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 7.1 °C/W
ψJB Junction-to-board characterization parameter 20 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.6 Electrical Characteristics

3.15 V ≤ VCC ≤ 3.45 V, VCC ≤ VCP ≤ 5.25 V, –40 °C ≤ TA ≤ 85 °C, except as specified. Typical values are at VCC = VCP = 3.3 V, 25 °C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ICC Current consumption All Vcc pins fPD = 10 MHz 45 mA
fPD = 100 MHz 50
fPD = 200 MHz 55
Vcp pin KPD = 0.1 mA 2
KPD = 1.6 mA 10
KPD = 3.1 mA 19
ICCPD Power down current POWERDOWN 3
fOSCin Frequency for OSCin terminal OSC_DIFFR = 0, doubler disabled 10 600 MHz
OSC_DIFFR = 0, doubler enabled 10 300
OSC_DIFFR = 1, doubler disabled 10 1200
OSC_DIFFR = 1, doubler enabled 10 600
VOSCin Voltage for OSCin pin(1) 0.5 VCC – 0.5 VPP
fFin Frequency for Fin pin 500 6400 MHz
PFin Power for Fin pin Single-ended operation –5 5 dBm
fPD Phase detector frequency 200 MHz
PN1Hz PLL figure of merit(2) –227 dBc/Hz
PN10kHz Normalized PLL 1/f noise(2) Normalized to 10-kHz offset for a 1-GHz carrier. –120 dBc/Hz
ICPoutTRI Charge pump leakage tri-state leakage 10 nA
ICPoutMM Charge pump mismatch(3) VCPout = VCP / 2 5%
ICPout Charge pump current VCPout = VCP / 2 CPG = 1X 0.1 mA
…
CPG = 31X 3.1
LOGIC OUTPUT TERMINALS (MUXout, TRIG1, TRIG2, MOD)
VOH Output high voltage 0.8 × VCC VCC V
VOL Output low voltage 0 0.2 × VCC V
LOGIC INPUT TERMINALS (CE, CLK, DATA, LE, MUXout, TRIG1, TRIG2, MOD)
VIH Input high voltage 1.4 VCC V
VIL Input low voltage 0 0.6 V
IIH Input leakage current –5 1 5 µA
tCELOW Chip enable low time 5 µs
tCEHIGH Chip enable high time 5 µs
(1) For optimal phase noise performance, higher input voltage and a slew rate of at least 3 V/ns is recommended
(2) PLL Noise Metrics are measured with a clean OSCin signal with a high slew rate using a wide loop bandwidth. The noise metrics model the PLL noise for an infinite loop bandwidth as:
PLL_Total = 10 × log( 10PLL_Flat / 10 + 10PLL_Flicker(Offset) / 10)
PLL_Flat = PN1Hz + 20 × log(N) + 10 × log(fPD / 1 Hz)
PLL_Flicker = PN10kHz - 10 × log(Offset / 10 kHz) + 20 × log(fVCO / 1 GHz)
(3) Charge pump mismatch varies as a function of charge pump voltage. Consult typical performance characteristics to see this variation.

6.7 Timing Requirements, Programming Interface (CLK, DATA, LE)

MIN TYP MAX UNIT
tCE Clock to LE low time 10 ns
tCS Data to clock setup time 4 ns
tCH Data to clock hold time 4 ns
tCWH Clock pulse width high 10 ns
tCWL Clock pulse width low 10 ns
tCES Enable to clock setup time 10 ns
tEWH Enable pulse width high 10 ns
LMX2491 TimDiag-01-SNAS711.gif Figure 1. Serial Data Input Timing

There are several other considerations for programming:

  • The DATA is clocked into a shift register on each rising edge of the CLK signal. On the rising edge of the LE signal, the data is sent from the shift register to an actual counter.
  • If no LE signal is given after the last data bit and the clock is kept toggling, then these bits are read into the next lower register. This eliminates the need to send the address each time.
  • A slew rate of at least 30 V/µs is recommended for the CLK, DATA, and LE signals
  • Timing specs also apply to readback. Readback can be done through the MUXout, TRIG1, TRIG2, or MOD terminals.

6.8 Typical Characteristics

LMX2491 tc03_cpout3V_snas624.png
Optimal performance is for a typical charge pump output voltage between 0.5 and 2.8 volts.
Figure 2. Charge Pump Current for VCP = 3.3 V
LMX2491 FSK-01-SNAS711.png
See Frequency Shift Keying Example for the detail of configuration.
Figure 4. Frequency Shift Keying
LMX2491 SawToo-01-SNAS711.png
See Continuous Sawtooth Ramp Example for the detail of configuration.
Figure 6. Continuous Sawtooth Ramp
LMX2491 Tri-01-SNAS711.png
See Continuous Triangular Ramp Example for the detail of configuration.
Figure 8. Continuous Triangular Ramp
LMX2491 Arb-01-SNAS711.png
See Arbitrary Waveform Ramp Example for the detail of configuration.
Figure 10. Arbitrary Waveform Ramp
LMX2491 tc04_cpout5V_snas624.png
Optimal performance is typically for a charge pump output voltage between 0.5 and 4.5 volts.
Figure 3. Charge Pump Current for VCP = 5.5 V
LMX2491 SawTooPul-01-SNAS711.png
See Single Sawtooth Ramp Example for the detail of configuration.
Figure 5. Single Sawtooth Ramp
LMX2491 SawFSK-01-SNAS711.png
See Continuous Sawtooth Ramp with FSK Example for the detail of configuration.
Figure 7. Continuous Sawtooth Ramp with FSK
LMX2491 Trap-01-SNAS711.png
See Continuous Trapezoid Ramp Example for the detail of configuration.
Figure 9. Continuous Trapezoid Ramp
LMX2491 ArbWF-01-SNAS711.png
See Arbitrary Waveform Ramp Example for the detail of configuration.
Figure 11. Output Flags