7.3.1 Reference Oscillator Input

Because the VCO frequency calibration algorithm is based on clocks from the OSCin pin, there are certain bits that need to be set depending on the OSCin frequency. XTLSEL (R6[22:20]) and XTLDIV (R7[9:8]) are both need to be set based on the OSCin frequency, f_OSCin. For some options and for low OSCin frequencies, the XTLMAN (R7[21:10]) and XTLMAN2 (R8[4]) words need to be set to the correct value.

7.3.2 R Divider

The R divider divides the OSCin frequency down to the phase detector frequency. The R divider value, R, is restricted to the values of 1, 2, 4, 8, 16, and 32. If R is greater than 8, then this also puts restrictions on the fractional denominator, FDEN, than can be used. This is discussed in greater depth in later sections.

7.3.3 Phase Detector and Charge Pump

The phase detector compares the outputs of the R and N dividers and puts out a correction current corresponding to the phase error. The phase detector frequency, f_PD, can be calculated as shown in Equation 1.

Choosing R = 1 yields the highest possible phase detector frequency and is optimum for phase noise, although there are restrictions on the maximum phase detector frequency which could force the R value to be larger. The far out PLL noise improves 3 dB for every doubling of the phase detector frequency, but at lower offsets, this effect is much less due to the PLL 1 / f noise. Aside from getting the best PLL phase noise, higher phase detector frequencies also make it easier to filter the noise that the delta-sigma modulator produces, which peaks at an offset frequency of f_PD / 2 from the carrier. The LMX2531 also has 16 levels of charge pump currents and a highly flexible fractional modulus. Increasing the charge pump current improves the phase noise about 3 dB per doubling of the charge pump current, although there are small diminishing returns as the charge pump current increases.

From a loop filter design and PLL phase noise perspective, one might think to always design with the highest possible phase detector frequency and charge pump current. However, if one considers the worst case fractional spurs that occur at an output frequency equal to 1 channel spacing away from a multiple of the f_OSCin, then this gives reason to reconsider. If the phase detector frequency or charge pump currents are too high, then these spurs could be degraded, and the loop filter may not be able to filter these spurs as well as theoretically predicted. For optimal spur performance, a phase detector frequency around 2.5 MHz and a charge pump current of 1X are recommended.

7.3.4 N Divider and Fractional Circuitry

The N divider in the LMX2531 includes fractional compensation and can achieve any fractional denominator between 1 and 4,194,303. The integer portion, N_Integer, is the whole part of the N divider value and the fractional portion, N_Fractional, is the remaining fraction. So in general, the total N divider value, N, is determined by Equation 2.

For example, if the phase detector frequency (f_PD) was 10 MHz and the VCO frequency (f_VCO) was 1736.1 MHz, then N would be 173.61. This would imply that N_Integer is 173 and N_Fractional is 61/100. N_Integer has some minimum value restrictions that are arise due to the architecture of this divider. The first restrictions arise because the N divider value is actually formed by a quadruple modulus 16/17/20/21 prescaler, which creates minimum divide values. N_Integer is further restricted because the LMX2531 due to the fractional engine of the N divider.

The fractional word, N_Fractional , is a fraction formed with the NUM and DEN words. In the example used here with the fraction of 61/100, NUM = 61 and DEN = 100. The fractional denominator value, DEN, can be set from 2 to 4,194,303. The case of DEN = 0 makes no sense, because this would cause an infinite N value; the case of 1 makes no sense either (but could be done), because integer mode should be used in these applications. All other values in this range, like 10, 32, 42, 734, or 4,000,000 are all valid. Once the fractional denominator, DEN, is determined, the fractional numerator, NUM, is intended to be varied from 0 to DEN-1.

In general, the fractional denominator, DEN, can be calculated by dividing the phase detector frequency by the greatest common divisor (GCD) of the channel spacing (f_CH) and the phase detector frequency. If the channel spacing is not obvious, then it can be calculated as the greatest common divisor of all the desired VCO frequencies.

For example, consider the case of a 10 MHz phase detector frequency and a 200 kHz channel spacing at the VCO output. The greatest common divisor of 10 MHz and 200 kHz is just 200 kHz. If one takes 10 MHz divided by 200 kHz, the result is 50. So a fractional denominator of 50, or any multiple of 50 would work in this example. Now consider a case with a 10 MHz phase detector frequency and a 30 kHz channel spacing. The greatest common divisor of 10 MHz and 30 kHz is 10 kHz. The fractional denominator therefore must be a multiple 1000, because this is 10 MHz divided by 10 kHz. For a final example, consider an application with a fixed output frequency of 2110.8 MHz and a OSCin frequency of 19.68 MHz. If the phase detector frequency is chosen to be 19.68 MHz, then the channel spacing can be calculated as the greatest common multiple of 19.68 MHz and 2110.8 MHz, which is 240 kHz. The fractional denominator is therefore a multiple of 41, which is 19.68 MHz / 240 kHz. Refer to AN-1865 Frequency Synthesis and Planning for PLL Architectures (SNAA061) for more details on frequency planning.

To achieve a fractional N value, an integer N divider is modulated between different values. This gives rise to three main degrees of freedom with the LMX2531 delta-sigma engine including the modulator order, dithering, and the way that the fractional portion is expressed. The first degree of freedom is the modulator order, which gives the user the ability to optimize for a particular application. The modulator order can be selected as zero (integer mode), two, three, or four. One simple technique to better understand the impact of the delta-sigma fractional engine on noise and spurs is to tune the VCO to an integer channel and observe the impact of changing the modulator order from integer mode to a higher order. The higher the fractional modulator order is, the lower the spurs theoretically are. However, this is not always the case, and the higher order fractional modulator can sometimes give rise to additional spurious tones, but this is dependent on the application. The second degree of freedom with the LMX2531 delta-sigma engine is dithering. Dithering is often effective in reducing these additional spurious tones, but can add phase noise in some situations. The third degree of freedom is the way that the fraction is expressed. For example, 1/10 can be expressed as 100000/1000000. Expressing the fraction in higher order terms sometimes improves the performance, particularly when dithering is used. In conclusion, there are some guidelines to getting the optimum choice of settings, but these optimum settings are application specific. Refer to AN-1879 Fractional N Frequency Synthesis (SNAA062) for a much more detailed discussion on fractional PLLs and fractional spurs.

7.3.5 Partially Integrated Loop Filter

The LMX2531 integrates the third pole (formed by R3 and C3) and fourth pole (formed by R4 and C4) of the loop filter. The values for C3, C4, R3, and R4 can also be programmed independently through the MICROWIRE interface and also R3 and R4 can be changed during FastLock, for minimum lock time. The larger the values of these components, the stronger the attenuation of the internal loop filter. The maximum attenuation can be achieved by setting R3 = R4 = 40 kΩ and C3 = C4 = 100 pF while the minimum attenuation is achieved by disabling the loop filter by setting EN_LPFLTR (R6[15]) to zero. Note that when the internal loop filter is disabled, there is still a small amount of input capacitance on front of the VCO on the order of 200 pF.

Because that the internal loop filter is on-chip, it is more effective at reducing certain spurs than the external loop filter. The higher order poles formed by the integrated loop filter are also helpful for attenuating noise due to the delta-sigma modulator. This noise produced by the delta-sigma modulator is outside the loop bandwidth and dependent on the modulator order. Although setting the filtering for maximum attenuation gives the best filtering, it puts increased restrictions on how wide the loop bandwidth of the system can be, which corresponds to the case where the shunt loop filter capacitor, C1, is zero. Increasing the charge pump current and/or the phase detector frequency increases the maximum attainable loop bandwidth when designing with the integrated filter. It is recommended to set the internal loop filter as high as possible without restricting the loop bandwidth of the system more than desired. If some setting between the minimum and maximum value is desired, it is preferable to reduce the resistor values before reducing the capacitor values because this will reduce the thermal noise contribution of the loop filter resistors. For design tools and more information on partially integrated loop filters, go to the Clock Design Tool on www.ti.com.

7.3.6 Low Noise, Fully Integrated VCO

The LMX2531 includes a fully integrated VCO, including the inductors. For optimum phase noise performance, this VCO has frequency and phase noise calibration algorithms. The frequency calibration algorithm is necessary because the VCO internally divides up the frequency range into several bands, to achieve a lower tuning gain, and therefore better phase noise performance. The frequency calibration routine is activated any time that the R0 register is programmed. There are several bits including LOCKMODE and XTLSEL that need to be set properly for this calibration to be performed in a reliable fashion. If the temperature shifts considerably and the R0 register is not programmed, then it cannot drift more than the maximum allowable drift for continuous lock, ΔT_CL, or else the VCO is not ensured to stay in lock. The phase noise calibration algorithm is necessary to achieve the lowest possible phase noise. Each version of the LMX2531, the VCO_ACI_SEL bit (R6[19:16]) needs to be set to the correct value to ensure the best possible phase noise.

The gain of the VCO can change considerably over frequency. It is lowest at the minimum frequency and highest at the maximum frequency. This range is specified in Electrical Characteristics of the data sheet. When designing the loop filter, the following method is recommended to determine what VCO gain to design to. First, take the geometric mean of the minimum and maximum frequencies that are to be used. Then use a linear approximation to extrapolate the VCO gain. Suppose the application requires the LMX2531LQ2080E PLL to tune from 2100 to 2150 MHz. The geometric mean of these frequencies is sqrt (2100 × 2150) MHz = 2125 MHz. The VCO gain is specified as 9 MHz/V at 1904 MHz and 20 MHz/V at 2274 MHz. Over this range of 370 MHz, the VCO gain changes 11 MHz/V. Therefore, at 2125 MHz, the VCO gain would be approximately 9 + (2125 – 1904) × 11 / 370 = 15.6 MHz/V. Although the VCO gain can change from part to part, this variation is small compared to how much the VCO gain can change over frequency.

The VCO frequency is related to the other frequencies and divider values as shown in Equation 4.

7.3.7 Programmable VCO Divider

All options of the LMX2531 offer the option of dividing the VCO output by two to get half of the VCO frequency at the Fout pin. The channel spacing at the Fout pin is also divided by two as well. Because this divide by two is outside feedback path between the VCO and the PLL, enabling does require one to change the N divider, R divider, or loop filter values. When this divider is enabled, there will be some far-out phase noise contribution to the VCO noise. Note that the R0 register should be reprogrammed the first time after the DIV2 bit is enabled or disabled for optimal phase noise performance. The frequency at the Fout pin is related to the VCO frequency and divider value, D, as shown in Equation 5.

7.3.8 Serial Data Timing Requirements

See MICROWIRE Timing Requirements.

Figure 2. Serial Data Timing Diagram

The DATA is clocked into a shift register on each rising edge of the CLK signal. On the rising edge of the LE signal, the data is sent from the shift registers to an actual counter. There are several other considerations as well:

• A slew rate of at least 30 V/μs is recommended for the CLK, DATA, and LE signals.
• After the programming is complete, the CLK, DATA, and LE signals should be returned to a low state.
• It is recommended to put a small delay between the falling edge of the last CLK pulse and the rising edge of the LE pulse for optimal noise immunity and the most reliable programming.
• Although it is strongly recommended to keep LE low after programming, LE can be kept high if bit R5[23] is changed to 0 (from its default value of 1). If this bit is changed, then the operation of the part is not ensured because it is not tested under these conditions.
• If the CLK and DATA lines are toggled while the in VCO is in lock, as is sometimes the case when these lines are shared with other parts, the phase noise may be degraded during the time of this programming.
• If the part is not programmed, the values of the registers in this part have to be assumed to be random. Therefore, the current consumption and spurs generated by this part can be random. If this is an issue, the CE pin can be held low for more consistent behavior.

Table 2. Register Location Truth Table

7.6.1 General Programming Information