SNAS252S October   2005  – December 2014 LMX2531

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 MICROWIRE Timing Requirements
    7. 6.7 Typical Performance Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Reference Oscillator Input
      2. 7.3.2 R Divider
      3. 7.3.3 Phase Detector and Charge Pump
      4. 7.3.4 N Divider and Fractional Circuitry
      5. 7.3.5 Partially Integrated Loop Filter
      6. 7.3.6 Low Noise, Fully Integrated VCO
      7. 7.3.7 Programmable VCO Divider
      8. 7.3.8 Serial Data Timing Requirements
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
    6. 7.6 Register Maps
      1. 7.6.1 General Programming Information
        1. 7.6.1.1  Initialization Sequence
        2. 7.6.1.2  Complete Register Content Map
        3. 7.6.1.3  Register R0
          1. 7.6.1.3.1 NUM[10:0] and NUM[21:12] -- Fractional Numerator
          2. 7.6.1.3.2 N[7:0] and N[10:8]
        4. 7.6.1.4  Register R1
          1. 7.6.1.4.1 NUM[21:12]
          2. 7.6.1.4.2 N[10:8] -- 3 MSB Bits for the N Counter
          3. 7.6.1.4.3 ICP[3:0] -- Charge Pump Current
        5. 7.6.1.5  Register R2
          1. 7.6.1.5.1 R[5:0] -- R Counter Value
          2. 7.6.1.5.2 DEN[21:12] and DEN[11:0]-- Fractional Denominator
        6. 7.6.1.6  Register R3
          1. 7.6.1.6.1 DEN[21:12] -- Extension for the Fractional Denominator
          2. 7.6.1.6.2 FoLD[3:0] -- Multiplexed Output for Ftest/LD Pin
          3. 7.6.1.6.3 ORDER -- Order of Delta-Sigma Modulator
          4. 7.6.1.6.4 DITHER -- Dithering
          5. 7.6.1.6.5 FDM -- Fractional Denominator Mode
          6. 7.6.1.6.6 DIV2
        7. 7.6.1.7  Register R4
          1. 7.6.1.7.1 TOC[13:0] -- Time-Out Counter for FastLock
          2. 7.6.1.7.2 ICPFL[3:0] -- Charge Pump Current for Fastlock
        8. 7.6.1.8  Register R5
          1. 7.6.1.8.1 EN_PLL -- Enable Bit for PLL
          2. 7.6.1.8.2 EN_VCO -- Enable Bit for the VCO
          3. 7.6.1.8.3 EN_OSC -- Enable Bit for the Oscillator Inverter
          4. 7.6.1.8.4 EN_VCOLDO -- Enable Bit for the VCO LDO
          5. 7.6.1.8.5 EN_PLLLDO1 -- Enable Bit for the PLL LDO 1
          6. 7.6.1.8.6 EN_PLLLDO2 -- Enable Bit for the PLL LDO 2
          7. 7.6.1.8.7 EN_DIGLDO -- Enable Bit for the digital LDO
          8. 7.6.1.8.8 REG_RST -- Resets All Registers to Default Settings
        9. 7.6.1.9  Register R6
          1. 7.6.1.9.1 C3_C4_ADJ[2:0] -- Value FOR C3 and C4 In The Internal Loop Filter
          2. 7.6.1.9.2 R3_ADJ_FL[1:0] -- Value for Internal Loop Filter Resistor R3 During Fastlock
          3. 7.6.1.9.3 R3_ADJ[1:0] -- Value for Internal Loop Filter Resistor R3
          4. 7.6.1.9.4 R4_ADJ_FL[1:0] -- Value for Internal Loop Filter Resistor R4 During Fastlock
          5. 7.6.1.9.5 R4_ADJ[1:0] -- Value for Internal Loop Filter Resistor R4
          6. 7.6.1.9.6 EN_LPFLTR-- Enable for Partially Integrated Internal Loop Filter
          7. 7.6.1.9.7 VCO_ACI_SEL
          8. 7.6.1.9.8 XTLSEL[2:0] -- OSCin Select
        10. 7.6.1.10 Register R7
          1. 7.6.1.10.1 XTLDIV[1:0] -- Division Ratio for the OSCin Frequency
          2. 7.6.1.10.2 XTLMAN[11:0] -- Manual OSCin Mode
        11. 7.6.1.11 Register R8
          1. 7.6.1.11.1 XTLMAN2 -- Manual Crystal Mode Second Adjustment
          2. 7.6.1.11.2 LOCKMODE -- Frequency Calibration Mode
        12. 7.6.1.12 Register R9
        13. 7.6.1.13 Register R12
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Do's and Don'ts
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Typical Connection Diagram
        1. 10.1.1.1 VccDIG, VccVCO, VccBUF, and VccPLL
        2. 10.1.1.2 VregDIG
        3. 10.1.1.3 VrefVCO
        4. 10.1.1.4 VregVCO
        5. 10.1.1.5 VregPLL1VregPLL2
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ

10 Layout

10.1 Layout Guidelines

For the layout of the LMX2531, perhaps the most important factor is to be aware of the package footprint. The asymmetrical land pattern can cause issues if not correctly done.

10.1.1 Typical Connection Diagram

10.1.1.1 VccDIG, VccVCO, VccBUF, and VccPLL

These pins are inputs to voltage regulators. Because the LMX2531 contains internal regulators, the power supply noise rejection is very good and capacitors at this pin are not critical. An RC filter can be used to reduce supply noise, but if the capacitor is too large and is placed too close to these pins, they can sometimes cause phase noise degradation in the 100 — 300 kHz offset range. Recommended values are from open to 1 μF. The 10 Ω series resistors serve to filter power supply noise and isolate these pins from large capacitances.

10.1.1.2 VregDIG

A bypass capacitor of 10 nF is recommended.

10.1.1.3 VrefVCO

If the VrefVCO capacitor is changed, it is recommended to keep this capacitor between 1/100 and 1/1000 of the value of the VregVCO capacitor.

10.1.1.4 VregVCO

Because this pin is the output of a regulator, there are stability concerns if there is not sufficient series resistance. For ceramic capacitors, the ESR (Equivalent Series Resistance) is too low, and it is recommended that a series resistance of 1 — 3.3 Ω is necessary. If there is insufficient ESR, then there may be degradation in the phase noise, especially in the 100 — 300 kHz offset. Recommended values are from 1 μF to 10 μF.

10.1.1.5 VregPLL1VregPLL2

The choice of the capacitor value at this pin involves a trade-off between integer spurs and phase noise in the 100 — 300 kHz offset range. Using a series resistor of about 220 mΩ in series with a capacitance that has an impedance of about 150 mΩ at the phase detector frequency seems to give an optimal trade-off. For instance, if the phase detector frequency is 2.5 MHz, then make this series capacitor 470 nF. If the phase detector frequency is 10 MHz, make this capacitance about 100 nF.

10.2 Layout Example

pcb_landpattern.png