SNAS252S October 2005 – December 2014 LMX2531
PRODUCTION DATA.
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
CE | 11 | Input | Chip Enable Input. High impedance CMOS input. This pin must not exceed 2.75 V. When CE is brought high the LMX2531 is powered up corresponding to the internal power control bits. Although the part can be programmed when powered down, it is still necessary to reprogram the R0 register to get the part to re-lock. |
CLK | 9 | Input | MICROWIRE clock input. High impedance CMOS input. This pin must not exceed 2.75 V. Data is clocked into the shift register on the rising edge. |
CPout | 24 | Output | Charge pump output for PLL. For connection to Vtune through an external passive loop filter. |
DATA | 8 | Input | MICROWIRE serial data input. High impedance CMOS input. This pin must not exceed 2.75 V. Data is clocked in MSB first. The last bits clocked in form the control or register select bits. |
FLout | 25 | Output | An open drain NMOS output which is used for FastLock or a general purpose output. |
Fout | 21 | Output | Buffered RF Output for the VCO. |
Ftest/LD | 30 | Output | Multiplexed CMOS output. Typically used to monitor PLL lock condition. |
GND | 3 | — | Ground |
GND | 19 | — | Ground for the VCO circuitry. |
GND | 20 | — | Ground for the VCO Output Buffer circuitry. |
GND | 34 | — | Ground |
LE | 10 | Input | MICROWIRE Latch Enable input. High impedance CMOS input. This pin must not exceed 2.75 V. Data stored in the shift register is loaded into the selected latch register when LE goes HIGH. |
NC | 2, 4, 5, 7, 12, 13, 29, 35 | — | No Connect. |
NC | 14, 15 | — | No Connect. Do NOT ground. This also includes the pad above these pins. |
OSCin | 31 | Input | Oscillator input. |
OSCin* | 32 | Input | Oscillator complimentary input. When a single ended source is used, then a bypass capacitor should be placed as close as possible to this pin and be connected to ground. |
Test | 33 | Output | This pin is for test purposes and should be grounded for normal operation. |
VccBUF | 22 | — | Power Supply for the VCO Buffer circuitry. Input may range from 2.8 — 3.2 V. Bypass capacitors should be placed as close as possible to this pin and ground. |
VccDIG | 1 | — | Power Supply for digital LDO circuitry. Input may range from 2.8 — 3.2 V. Bypass capacitors should be placed as close as possible to this pin and ground. |
VccPLL | 27 | — | Power Supply for the PLL. Input may range from 2.8 — 3.2 V. Bypass capacitors should be placed as close as possible to this pin and ground. |
VccVCO | 16 | — | Power Supply for VCO regulator circuitry. Input may range from 2.8 — 3.2 V. Bypass capacitors should be placed as close as possible to this pin and ground. |
VrefVCO | 18 | — | Internal reference voltage for VCO LDO. Not intended to drive an external load. Connect to ground with a capacitor. |
VregBUF | 6 | — | Internally regulated voltage for the VCO buffer circuitry. Connect to ground with a capacitor. |
VregDIG | 36 | — | Internally regulated voltage for LDO digital circuitry. |
VregPLL1 | 26 | — | Internally regulated voltage for PLL charge pump. Not intended to drive an external load. Connect to ground with a capacitor. |
VregPLL2 | 28 | — | Internally regulated voltage for RF digital circuitry. Not intended to drive an external load. Connect to ground with a capacitor. |
VregVCO | 17 | — | Internally regulated voltage for VCO circuitry. Not intended to drive an external load. Connect to ground with a capacitor and some series resistance. |
Vtune | 23 | Input | Tuning voltage input for the VCO. For connection to the CPout pin through an external passive loop filter. |