JAJSE32B October 2017 – January 2019 LMX2572
PRODUCTION DATA.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SYSREF_DIV_PRE | SYSREF_PULSE | SYSREF_EN | SYSREF_REPEAT | 0 | 1 | ||
R/W-0h | R/W-4h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 - 8 | R/W | 0h | Program 0h to this field. | |
7 - 5 | SYSREF_DIV_PRE | R/W | 4h | This divider is used to get the frequency input to the Post-SR divider within acceptable limits. See Application for SYSREF for details.
2: Divide by 2 4: Divide by 4 All other values are invalid. |
4 | SYSREF_PULSE | R/W | 0h | When in master mode (SYSREF_REPEAT = 0), this allows multiple pulses (as determined by SYSREF_PULSE_CNT) to be sent out whenever the SysRefReq pin goes high.
0: Disabled 1: Enabled |
3 | SYSREF_EN | R/W | 0h | Enables SYSREF mode.
0: Disabled 1: Enabled |
2 | SYSREF_REPEAT | R/W | 0h | Defines SYSREF mode.
0: Master mode. In this mode, SYSREF pulses are generated continuously at the output. 1: Repeater Mode. In this mode, SYSREF pulses are generated in response to the SysRefReq pin. |
1 - 0 | R/W | 0h | Program 1h to this field. |