JAJSDN8C March   2017  – April 2019 LMX2594

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Reference Oscillator Input
      2. 8.3.2  Reference Path
        1. 8.3.2.1 OSCin Doubler (OSC_2X)
        2. 8.3.2.2 Pre-R Divider (PLL_R_PRE)
        3. 8.3.2.3 Programmable Multiplier (MULT)
        4. 8.3.2.4 Post-R Divider (PLL_R)
        5. 8.3.2.5 State Machine Clock
      3. 8.3.3  PLL Phase Detector and Charge Pump
      4. 8.3.4  N-Divider and Fractional Circuitry
      5. 8.3.5  MUXout Pin
        1. 8.3.5.1 Lock Detect
        2. 8.3.5.2 Readback
      6. 8.3.6  VCO (Voltage-Controlled Oscillator)
        1. 8.3.6.1 VCO Calibration
        2. 8.3.6.2 Determining the VCO Gain
      7. 8.3.7  Channel Divider
      8. 8.3.8  Output Buffer
      9. 8.3.9  Power-Down Modes
      10. 8.3.10 Phase Synchronization
        1. 8.3.10.1 General Concept
        2. 8.3.10.2 Categories of Applications for SYNC
        3. 8.3.10.3 Procedure for Using SYNC
        4. 8.3.10.4 SYNC Input Pin
      11. 8.3.11 Phase Adjust
      12. 8.3.12 Fine Adjustments for Phase Adjust and Phase SYNC
      13. 8.3.13 Ramping Function
        1. 8.3.13.1 Manual Pin Ramping
          1. 8.3.13.1.1 Manual Pin Ramping Example
        2. 8.3.13.2 Automatic Ramping
          1. 8.3.13.2.1 Automatic Ramping Example (Triangle Wave)
      14. 8.3.14 SYSREF
        1. 8.3.14.1 Programmable Fields
        2. 8.3.14.2 Input and Output Pin Formats
          1. 8.3.14.2.1 Input Format for SYNC and SysRefReq Pins
          2. 8.3.14.2.2 SYSREF Output Format
        3. 8.3.14.3 Examples
        4. 8.3.14.4 SYSREF Procedure
      15. 8.3.15 SysRefReq Pin
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
      1. 8.5.1 Recommended Initial Power-Up Sequence
      2. 8.5.2 Recommended Sequence for Changing Frequencies
      3. 8.5.3 General Programming Requirements
    6. 8.6 Register Maps
      1. 8.6.1  General Registers R0, R1, & R7
        1. Table 24. Field Descriptions
      2. 8.6.2  Input Path Registers
        1. Table 25. Field Descriptions
      3. 8.6.3  Charge Pump Registers (R13, R14)
        1. Table 26. Field Descriptions
      4. 8.6.4  VCO Calibration Registers
        1. Table 27. Field Descriptions
      5. 8.6.5  N Divider, MASH, and Output Registers
        1. Table 28. Field Descriptions
      6. 8.6.6  SYNC and SysRefReq Input Pin Register
        1. Table 29. Field Descriptions
      7. 8.6.7  Lock Detect Registers
        1. Table 30. Field Descriptions
      8. 8.6.8  MASH_RESET
        1. Table 31. Field Descriptions
      9. 8.6.9  SysREF Registers
        1. Table 32. Field Descriptions
      10. 8.6.10 CHANNEL Divider Registers
        1. Table 33. Field Descriptions
      11. 8.6.11 Ramping and Calibration Fields
        1. Table 34. Field Descriptions
      12. 8.6.12 Ramping Registers
        1. 8.6.12.1 Ramp Limits
          1. Table 35. Field Descriptions
        2. 8.6.12.2 Ramping Triggers, Burst Mode, and RAMP0_RST
          1. Table 36. Field Descriptions
        3. 8.6.12.3 Ramping Configuration
          1. Table 37. Field Descriptions
      13. 8.6.13 Readback Registers
        1. Table 38. Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 OSCin Configuration
      2. 9.1.2 OSCin Slew Rate
      3. 9.1.3 RF Output Buffer Power Control
      4. 9.1.4 RF Output Buffer Pullup
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 12.1.2 開発サポート
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.6.12.3 Ramping Configuration

Figure 48. Registers Excluding Address
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
R98 RAMP0_INC[29:16] 0 RAMP0_DLY
R99 RAMP0_INC[15:0]
R100 RAMP0_LEN
R101 0 0 0 0 0 0 0 0 0 RAMP1
_DLY		 RAMP1
_RST		 RAMP0
_NEXT		 0 0 RAMP0_
NEXT_TRIG
R102 0 0 RAMP1_INC[29:16]
R103 RAMP1_INC[15:0]
R104 RAMP1_LEN
R105 RAMP_DLY_CNT RAMP
_MANUAL		 RAMP1
_NEXT		 0 0 RAMP1_
NEXT_TRIG
R106 0 0 0 0 0 0 0 0 0 0 0 RAMP_TRIG_CAL 0 RAMP_SCALE_COUNT
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 37. Field Descriptions

Location Field Type Reset Description
R98[15:2]
R99[15:0]		 RAMP0_INC R/W 0 2's complement of the amount the RAMP0 is incremented in phase detector cycles.
R98[0] RAMP0_DLY R/W 0 Enabling this bit uses two clocks instead of one to clock the ramp. Effectively doubling the length.
0: Normal ramp length
1: Double ramp length
R100[15:0] RAMP0_LEN R/W 0 Length of RAMP0 in phase detector cycles
R101[6] RAMP1_DLY R/W 0 Enabling this bit uses two clocks instead of one to clock the ramp. Effectively doubling the length.
0: Normal ramp length
1: Double ramp length
R101[5] RAMP1_RST R/W 0 Resets RAMP1 to eliminate rounding errors. Must be used in automatic ramping mode.
0: Disabled
1: Enabled
R101[4] RAMP0_NEXT R/W 0 Defines what ramp comes after RAMP0
0: RAMP0
1: RAMP1
R101[1:0] RAMP0_NEXT_TRIG R/W 0 Defines what triggers the next ramp
0: RAMP0_LEN timeout counter
1: Trigger A
2: Trigger B
3: Reserved
R102[13:0]
R103[15:0]		 RAMP1_INC R/W 0 2's complement of the amount the RAMP1 is incremented in phase detector cycles.
R104[15:0] RAMP1_LEN R/W 0 Length of RAMP1 in phase detector cycles
R105[15:6] RAMP_DLY_CNT R/W 0 This is the number of state machine clock cycles for the VCO calibration in automatic mode. If the VCO calibration is less, then it is this time. If it is more, then the time is the VCO calibration time.
R105[5] RAMP_MANUAL R/W 0 Enables manual ramping mode, or otherwise automatic mode
0: Automatic ramping mode
1: Manual ramping mode
R105[4] RAMP1_NEXT R/W 0 Determines what ramp comes after RAMP1:
0: RAMP0
1: RAMP1
R105[1:0] RAMP1_NEXT_TRIG R/W 0 Defines what triggers the next ramp
0: RAMP1_LEN timeout counter
1: Trigger A
2: Trigger B
3: Reserved
R106[4] RAMP_TRIG_CAL R/W 0 Enabling this bit forces the VCO to calibrate after the ramp.
R106[2:0] RAMP_SCALE_COUNT R/W 7 Multiplies RAMP_DLY count by 2RAMP_SCALE_COUNT