JAJSFA2C September   2014  – April 2018 LP5907-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Output and Input Capacitors
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 LP5907-Q1 Voltage Options
      2. 7.3.2 Enable (EN)
      3. 7.3.3 Low Output Noise
      4. 7.3.4 Output Automatic Discharge
      5. 7.3.5 Remote Output Capacitor Placement
      6. 7.3.6 Thermal Overload Protection (TSD)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Enable (EN)
      2. 7.4.2 Minimum Operating Input Voltage (VIN)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Power Dissipation and Device Operation
        2. 8.2.2.2 External Capacitors
        3. 8.2.2.3 Input Capacitor
        4. 8.2.2.4 Output Capacitor
        5. 8.2.2.5 Capacitor Characteristics
        6. 8.2.2.6 Remote Capacitor Operation
        7. 8.2.2.7 No-Load Stability
        8. 8.2.2.8 Enable Control
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントの更新通知を受け取る方法
    2. 11.2 コミュニティ・リソース
    3. 11.3 商標
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

DBV Package
5-Pin SOT-23
(Top View)
LP5907-Q1 pinout_snvsa34.gif

Pin Functions

PIN I/O DESCRIPTION
NAME SOT23-5
IN 1 I Input voltage supply. Connect a 1-µF capacitor at this input.
GND 2 – Common ground
EN 3 I Enable input. A low voltage (< VIL) on this pin turns the regulator off and discharges the output pin to GND through an internal 230-Ω pulldown resistor. A high voltage (> VIH) on this pin enables the regulator output. This pin has an internal 1-MΩ pulldown resistor to hold the regulator off by default.
N/C 4 – No internal electrical connection.
OUT 5 O Regulated output voltage. Connect a minimum 1-µF low-ESR capacitor to this pin. Connect this output to the load circuit. An internal 230-Ω (typical) pulldown resistor prevents a charge remaining on VOUT when the regulator is in the shutdown mode (VEN low).