JAJSG11E October   2014  – December 2019 MSP430FR4131 , MSP430FR4132 , MSP430FR4133

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
      1. Table 4-1 Signal Descriptions
    3. 4.3 Pin Multiplexing
    4. 4.4 Connection of Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Active Mode Supply Current Per MHz
    6. 5.6  Low-Power Mode LPM0 Supply Currents Into VCC Excluding External Current
    7. 5.7  Low-Power Mode LPM3, LPM4 Supply Currents (Into VCC) Excluding External Current
    8. 5.8  Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
    9. 5.9  Typical Characteristics, Low-Power Mode Supply Currents
    10. 5.10 Typical Characteristics, Current Consumption Per Module
    11. 5.11 Thermal Characteristics
    12. 5.12 Timing and Switching Characteristics
      1. 5.12.1  Power Supply Sequencing
        1. Table 5-1 PMM, SVS and BOR
      2. 5.12.2  Reset Timing
        1. Table 5-2 Wake-up Times From Low-Power Modes and Reset
      3. 5.12.3  Clock Specifications
        1. Table 5-3 XT1 Crystal Oscillator (Low Frequency)
        2. Table 5-4 DCO FLL, Frequency
        3. Table 5-5 REFO
        4. Table 5-6 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        5. Table 5-7 Module Oscillator Clock (MODCLK)
      4. 5.12.4  Digital I/Os
        1. Table 5-8 Digital Inputs
        2. Table 5-9 Digital Outputs
        3. 5.12.4.1  Digital I/O Typical Characteristics
      5. 5.12.5  Timer_A
        1. Table 5-10 Timer_A
      6. 5.12.6  eUSCI
        1. Table 5-11 eUSCI (UART Mode) Operating Frequency
        2. Table 5-12 eUSCI (UART Mode) Switching Characteristics
        3. Table 5-13 eUSCI (SPI Master Mode) Operating Frequency
        4. Table 5-14 eUSCI (SPI Master Mode) Switching Characteristics
        5. Table 5-15 eUSCI (SPI Slave Mode) Switching Characteristics
        6. Table 5-16 eUSCI (I2C Mode) Switching Characteristics
      7. 5.12.7  ADC
        1. Table 5-17 ADC, Power Supply and Input Range Conditions
        2. Table 5-18 ADC, 10-Bit Timing Parameters
        3. Table 5-19 ADC, 10-Bit Linearity Parameters
      8. 5.12.8  LCD Controller
        1. Table 5-20 LCD Recommended Operating Conditions
      9. 5.12.9  FRAM
        1. Table 5-21 FRAM
      10. 5.12.10 Emulation and Debug
        1. Table 5-22 JTAG and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1  CPU
    2. 6.2  Operating Modes
    3. 6.3  Interrupt Vector Addresses
    4. 6.4  Bootloader (BSL)
    5. 6.5  JTAG Standard Interface
    6. 6.6  Spy-Bi-Wire Interface (SBW)
    7. 6.7  FRAM
    8. 6.8  Memory Protection
    9. 6.9  Peripherals
      1. 6.9.1  Power Management Module (PMM) and On-Chip Reference Voltages
      2. 6.9.2  Clock System (CS) and Clock Distribution
      3. 6.9.3  General-Purpose Input/Output Port (I/O)
      4. 6.9.4  Watchdog Timer (WDT)
      5. 6.9.5  System Module (SYS)
      6. 6.9.6  Cyclic Redundancy Check (CRC)
      7. 6.9.7  Enhanced Universal Serial Communication Interface (eUSCI_A0, eUSCI_B0)
      8. 6.9.8  Timers (Timer0_A3, Timer1_A3)
      9. 6.9.9  Real-Time Clock (RTC) Counter
      10. 6.9.10 10-Bit Analog Digital Converter (ADC)
      11. 6.9.11 Liquid Crystal Display (LCD)
      12. 6.9.12 Embedded Emulation Module (EEM)
      13. 6.9.13 Input/Output Schematics
        1. 6.9.13.1  Port P1 Input/Output With Schmitt Trigger
        2. 6.9.13.2  Port P2 Input/Output With Schmitt Trigger
        3. 6.9.13.3  Port P3 Input/Output With Schmitt Trigger
        4. 6.9.13.4  Port P4.0 Input/Output With Schmitt Trigger
        5. 6.9.13.5  Port P4.1 and P4.2 Input/Output With Schmitt Trigger
        6. 6.9.13.6  Port 4.3, P4.4, P4.5, P4.6, and P4.7 Input/Output With Schmitt Trigger
        7. 6.9.13.7  Port P5.0, P5.1, P5.2, and P5.3 Input/Output With Schmitt Trigger
        8. 6.9.13.8  Port P5.4, P5.5, P5.6, and P5.7 Input/Output With Schmitt Trigger
        9. 6.9.13.9  Port P6 Input/Output With Schmitt Trigger
        10. 6.9.13.10 Port P7 Input/Output With Schmitt Trigger
        11. 6.9.13.11 Port P8.0 and P8.1 Input/Output With Schmitt Trigger
        12. 6.9.13.12 Port P8.2 and P8.3 Input/Output With Schmitt Trigger
    10. 6.10 Device Descriptors (TLV)
    11. 6.11 Memory
      1. 6.11.1 Peripheral File Map
    12. 6.12 Identification
      1. 6.12.1 Revision Identification
      2. 6.12.2 Device Identification
      3. 6.12.3 JTAG Identification
  7. 7Applications, Implementation, and Layout
    1. 7.1 Device Connection and Layout Fundamentals
      1. 7.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 7.1.2 External Oscillator
      3. 7.1.3 JTAG
      4. 7.1.4 Reset
      5. 7.1.5 Unused Pins
      6. 7.1.6 General Layout Recommendations
      7. 7.1.7 Do's and Don'ts
    2. 7.2 Peripheral- and Interface-Specific Design Information
      1. 7.2.1 ADC Peripheral
        1. 7.2.1.1 Partial Schematic
        2. 7.2.1.2 Design Requirements
        3. 7.2.1.3 Layout Guidelines
      2. 7.2.2 LCD_E Peripheral
        1. 7.2.2.1 Partial Schematic
        2. 7.2.2.2 Design Requirements
        3. 7.2.2.3 Detailed Design Procedure
        4. 7.2.2.4 Layout Guidelines
    3. 7.3 Typical Applications
  8. 8デバイスおよびドキュメントのサポート
    1. 8.1  はじめに
    2. 8.2  デバイスの項目表記
    3. 8.3  ツールとソフトウェア
    4. 8.4  ドキュメントのサポート
    5. 8.5  関連リンク
    6. 8.6  Community Resources
    7. 8.7  商標
    8. 8.8  静電気放電に関する注意事項
    9. 8.9  Export Control Notice
    10. 8.10 Glossary
  9. 9メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

1 デバイスの概要